Oxide TFT Substrate Etch Stopper Reduces Mask Processes
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Solution Overview
Problem
The manufacturing process for thin film transistor substrates with oxide semiconductor materials in fringe field type liquid crystal displays is complex and costly due to the need for multiple mask processes, which complicates the production and increases the risk of errors and costs.
Innovation Solution
A method to simplify the manufacturing process by using an etch stopper as a mask to define the channel area, reducing the number of mask processes required, and integrating the data element and etch stopper in a single process, allowing for the formation of a thin film transistor substrate with an oxide semiconductor layer using only 4 mask processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to manufacture thin film transistor substrates with oxide semiconductor materials, then the manufacturing precision and reliability are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the etch stopper layer and data element into a single integrated structure formed through one mask process. This merging eliminates the need for separate mask processes that would otherwise be required to form the etch stopper and data element independently, thereby reducing overall process complexity while maintaining manufacturing precision
Solution Approach 2:
The etch stopper layer serves multiple functions: it acts as an etch stop during processing, defines the channel area boundary, and serves as the base for the data element. This multi-functionality eliminates the need for separate structures and processes, reducing device complexity while maintaining precise control over channel formation
2Manufacturing precision
If multiple mask processes are used to define channel area, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent merges the channel area definition function into the single mask process that forms the etch stopper and data element. By combining multiple functions (etch stopping, channel definition, data element formation) into one process step, the patent maintains precise channel area definition while eliminating redundant processing steps that would reduce productivity
3Productivity
If the channel length is minimized to enhance integration density, then the productivity and integration density are improved, but the manufacturing precision requirements increase
Solution Approach 1:
The etch stopper structure automatically defines the channel area boundary through its geometric configuration. The channel length is self-determined by the etch stopper dimensions and the etching process, eliminating the need for additional precision-critical alignment steps. This self-defining mechanism enables minimal channel lengths while maintaining manufacturing precision
Solution Approach 2:
The etch stopper is formed in advance with predetermined dimensions that directly define the future channel area. This preliminary formation of the boundary structure allows subsequent processes to simply follow the pre-defined geometry, reducing precision requirements for later steps while enabling minimal channel lengths
Data Source
AI summary
The present disclosure relates to a thin film transistor substrate having a metal oxide semiconductor for the fringe field type flat panel displays and a method for manufacturing the same. The thin film transistor substrate having an oxide semiconductor layer can include a substrate including pixel region; a gate element formed on the substrate; a gate insulating layer covering the gate element; a channel layer on the gate insulating layer, a source area expanded form a first side of the channel layer, a drain area expanded from a second side of the channel layer, and a pixel electrode expanded from the drain area to the pixel region; an etch stopper formed on the channel layer; a data element formed on the etch stopper; and a common electrode formed on the passivation layer and within the pixel region.