Semiconductor Pillar Gate Segmentation for GIDL Reduction
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Solution Overview
Problem
There is a demand for semiconductor devices that are compact in size and consume low electric power, with a need to increase integration density while minimizing device size and reducing gate-induced drain leakage (GIDL) effects.
Innovation Solution
The semiconductor device design includes trench isolation regions, semiconductor pillars, gate lines, and conductive patterns on a substrate, with specific impurity regions and insulating layers to enhance integration density and reduce GIDL, along with methods for fabricating these devices that involve forming trench isolation regions, semiconductor pillars, and conductive patterns to achieve compactness and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of elements constituting the semiconductor device is reduced to increase integration density, then the device becomes more compact and integration density improves, but gate-induced drain leakage (GIDL) effects increase
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate line and second gate line) that are positioned at different heights and locations. This segmentation allows each gate to control specific regions of the semiconductor pillars independently, enabling better suppression of GIDL in miniaturized devices while maintaining high integration density through the multi-gate configuration.
Solution Approach 2:
The patent introduces a vertical dimension to the gate structure by positioning the first gate line and second gate line at different heights above the substrate. This three-dimensional gate arrangement allows control over the channel from multiple vertical levels, effectively suppressing GIDL effects that become prominent in scaled-down devices while maintaining compact footprint for high integration density.
2Area of moving object
If the device size is reduced to create compact semiconductor devices, then the device footprint decreases, but manufacturing complexity increases due to multiple gate lines and conductive patterns
Solution Approach 1:
Multiple conductive patterns are merged and integrated into a unified gate structure where the first gate line and second gate line are formed as part of the same fabrication sequence. The conductive patterns connecting the gates to the semiconductor pillars are integrated into the overall device architecture, reducing the number of separate fabrication steps while maintaining the multi-gate configuration for compact device footprint.
Solution Approach 2:
The gate lines and conductive patterns serve multiple functions: they provide electrical control over the semiconductor pillars, act as interconnect elements, and define the active regions of the device. This multi-functionality reduces the need for separate dedicated structures for each function, thereby simplifying the manufacturing process while maintaining compact device dimensions.
Data Source
AI summary
A semiconductor device includes a trench isolation region provided on a substrate and defining first and second active regions separated from each other. A first semiconductor pillar protruding upward from the first active region is provided. A second semiconductor pillar protruding upward from the second active region is provided. A first gate mask extending to cross over the first and second active regions is provided. The first gate mask surrounds upper sidewalls of the first and second semiconductor pillars. A first gate line formed below the first gate mask, separated from the first and second active regions, and surrounding parts of sidewalls of the first and second semiconductor pillars is provided.