Sealed Cavity Structures with Planar Surface for RF Linearity
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Solution Overview
Problem
The high cost of manufacturing radio frequency (RF) devices on trap rich silicon on insulator (SOI) wafers due to their expensive nature, which is up to 50% of the total manufacturing cost, and the performance degradation of devices built on bulk Si substrates due to degraded linearity, harmonics, noise, and leakage currents.
Innovation Solution
The formation of sealed cavity structures in bulk silicon wafers using a trench filled with a first material that reflows under a second material, creating a planar surface, which reduces manufacturing costs and improves device performance by providing excellent linearity and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI wafers are used to achieve excellent vertical isolation and linearity, then device performance is improved, but manufacturing cost increases significantly
Solution Approach 1:
The substrate is segmented into two distinct regions: a bulk silicon region providing RF linearity and a separate SOI region providing vertical isolation. This segmentation allows each region to fulfill its specific function without requiring the entire substrate to be expensive SOI material, thereby reducing overall manufacturing cost while maintaining performance.
Solution Approach 2:
Different regions of the substrate are assigned different material properties tailored to their specific functions. The bulk silicon region is optimized for RF linearity while the SOI region is optimized for vertical isolation. This local differentiation allows cost-effective material selection in each zone, avoiding the need for expensive SOI throughout the entire substrate area.
2Ease of manufacture
If bulk Si substrates are used to reduce manufacturing cost, then cost decreases, but device performance degrades due to degraded linearity, harmonics, noise, and leakage currents
Solution Approach 1:
The substrate is divided into bulk silicon and SOI regions, with the bulk silicon providing the necessary RF linearity at lower cost. By segmenting the substrate functionality, the patent achieves acceptable linearity performance without requiring expensive SOI material throughout, thus resolving the cost-performance tradeoff.
Solution Approach 2:
The bulk silicon region is specifically designed and doped to provide optimal RF linearity characteristics where needed, while other regions use different materials for their specific functions. This local optimization allows cost-effective bulk silicon to achieve the required linearity performance in critical areas.
3Object-affected harmful factors
If SOI wafers are used to achieve excellent vertical isolation, then isolation performance is improved, but manufacturing cost increases by up to 50%
Solution Approach 1:
Vertical isolation functionality is segmented to only the regions where it is critically needed, using localized SOI structures rather than requiring SOI throughout the entire substrate. This selective segmentation maintains necessary isolation performance while minimizing the area of expensive material used.
Solution Approach 2:
SOI material is applied locally only in regions requiring superior vertical isolation, while bulk silicon is used in regions where isolation is less critical. This local application of SOI material achieves necessary isolation performance while dramatically reducing the overall material cost compared to full-SOI substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of RF devices with improved linearity and reduced manufacturing costs by using bulk silicon wafers, achieving performance comparable to SOI wafers while lowering the normalized manufacturing cost.
Implementation Method 1
filling a top portion of the trench with a first material; and covering the trench with a second material at a certain temperature such that the first material reflows within the trench forming a cavity within the substrate material which has a shape different than the trench prior to the covering of the trench
Implementation Method 2
the cavity being covered with epitaxial material that has an upper planar surface
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.