Tri-Gate and Dual-Gate FinFET Fabrication on SOI
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional CMOS devices face challenges in maintaining high drive current with low leakage and threshold stability as they approach scaling limits, particularly due to lateral short channel effects and vertical gate insulator tunneling leakage current, necessitating alternative gate stack materials and transistor structures like FinFETs on silicon-on-insulator (SOI) substrates.
Innovation Solution
A method for fabricating dual-gate and tri-gate FinFETs on the same SOI substrate, involving impurity implantation, hard mask patterning, gate dielectric formation, and conductive layer etching to create independent gate electrodes for enhanced control over channel regions, allowing for adjustable threshold voltages and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CMOS devices are scaled down to nanometer regime, then device density and integration are improved, but drive current and threshold stability deteriorate due to lateral short channel effects and gate insulator tunneling leakage
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical channels. The channel region extends vertically from the substrate surface, creating a fins-like structure that provides better gate control over the channel while maintaining scaled dimensions. This dimensional change enables continued scaling while improving threshold stability and reducing short channel effects.
Solution Approach 2:
The patent employs composite material structures including silicon-on-insulator (SOI) substrates with silicon fin regions, silicon nitride hard masks, silicon oxide gate dielectric layers, and polysilicon gate electrodes. These composite materials provide the necessary electrical, mechanical, and chemical properties for achieving both high density and reliable threshold control in scaled devices.
2Productivity
If gate length is reduced to circumvent tunneling restriction, then device scaling is improved, but gate control over channel deteriorates due to lateral short channel effects
Solution Approach 1:
The patent introduces vertical channel structures where the channel extends from the substrate surface upward to form fins. The gate electrode wraps around the fin structure, providing control from multiple directions (front, back, and sides). This three-dimensional gate configuration maintains effective gate control even as horizontal dimensions are scaled down, circumventing lateral short channel effects.
3Adaptability or versatility
If different threshold voltages are required for different circuits, then circuit performance is improved, but manufacturing complexity increases due to separate fabrication processes for tri-gate and dual-gate FinFETs
Solution Approach 1:
The patent divides the semiconductor substrate into multiple regions, with each region containing FinFET structures configured for specific threshold voltage requirements. Tri-gate FinFETs (with gates on three sides) are fabricated in regions requiring higher drive current, while dual-gate FinFETs (with gates on two sides) are fabricated in regions requiring lower leakage. This spatial segmentation allows different device characteristics coexist on the same substrate using a unified fabrication approach.
Solution Approach 2:
The patent implements local variations in gate configuration within different substrate regions. By selectively forming tri-gate or dual-gate structures in specific locations based on circuit requirements, the patent achieves locally optimized device characteristics. This allows high-current I/O circuits to use tri-gate FinFETs while core logic circuits use dual-gate FinFETs, all on the same chip.
4Reliability
If FinFET structures are used to improve gate control, then threshold stability is improved, but device structure complexity increases
Solution Approach 1:
The patent implements vertical fin structures that extend upward from the substrate, transforming the traditional planar device architecture into a three-dimensional configuration. The gate electrode wraps around the fin, providing control from front, back, and lateral surfaces. This vertical dimension enables superior gate control and threshold stability while the fabrication process uses sequential deposition and etching steps that manage structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the simultaneous fabrication of tri-gate FinFETs for high current drive I/O devices and dual-gate FinFETs for low leakage core logic devices, offering increased circuit design flexibility and dynamic modulation of device characteristics like threshold voltage and sub-threshold swing.
Implementation Method 1
implanting impurities into the semiconductor layer for adjusting a threshold voltage
Implementation Method 2
etching the semiconductor layer using the first and second hard mask cap portions as a mask to form a first fin and a second fin
Implementation Method 3
planarizing the interlayer dielectric layer using a chemical mechanical polishing process back to the upper surface of the first hard mask cap portion
Data Source
AI summary
A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.