Vertical Transistor Fabrication Preventing Floating Body Effect
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Solution Overview
Problem
The floating body effect in semiconductor devices with vertical surrounding gate structures, particularly when the gate length exceeds 40 nanometers, leads to charge accumulation, influencing threshold voltage, increasing drain current, and causing automatic device activation and current leakage, which compromises reliability and stability.
Innovation Solution
A method for fabricating a vertical transistor with a surrounding gate structure that includes forming a substrate with protruding pillars, a patterned layer, a gate dielectric layer, and a base line on one side, and a second doped region on the other side, effectively preventing the floating body effect by using ion implantation and conductive layers to create a better channel control capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertical surrounding gate structure is used to improve channel control capability, then device performance is improved, but floating body effect occurs causing current leakage and reliability issues
Solution Approach 1:
The gate structure is segmented into multiple parts: a first gate electrode and a second gate electrode separated by a first dielectric layer, with additional bit lines and base lines providing further segmentation. This segmentation allows independent control of different regions, preventing charge accumulation that causes floating body effect while maintaining channel control capability.
Solution Approach 2:
A first dielectric layer is introduced as an intermediary between the first gate electrode and the second gate electrode. This dielectric layer electrically isolates the two gate electrodes, preventing unwanted electrical interaction and charge accumulation, thereby eliminating the floating body effect while preserving the vertical surrounding gate's channel control advantages.
2Stability of the object's composition
If gate length is increased beyond 40 nanometers, then device stability is improved, but floating body effect becomes more severe
Solution Approach 1:
The gate structure is divided into multiple segments along the channel length, with the first gate electrode covering a first region and the second gate electrode covering a second region. This segmentation along the longitudinal axis allows each segment to independently manage charge distribution, preventing the severe floating body effect that occurs in long-channel devices while maintaining overall device stability.
Solution Approach 2:
Different regions of the gate structure are given different electrical characteristics through the segmentation into first and second gate electrodes with separate control. This allows local optimization of charge distribution in different parts of the channel, preventing floating body effect in specific regions while maintaining stability throughout the entire device.
3Manufacturing precision
If ion implantation is used to form doped regions, then channel control is improved, but manufacturing complexity increases
Solution Approach 1:
Doped regions are formed in the substrate before the gate electrodes and dielectric layers are constructed. This preliminary formation of doped source and drain regions simplifies subsequent processing steps, as the ion implantation is completed early in the manufacturing sequence rather than requiring complex later-stage doping operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability and stability of the device by preventing current leakage and improving channel control, ensuring the transistor operates correctly without unintended activation, even when no voltage is applied.
Implementation Method 1
a first doped region is formed in a lower part of the pillar... A second doped region is formed in the upper part of the pillar... a method of forming the first doped region includes ion implantation... The method of forming the second doped region includes ion implantation
Data Source
AI summary
A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and the lower part has a first doped region. A gate dielectric layer is formed on a sidewall at one side of the pillar. A surrounding gate is formed on the gate dielectric layer located on the channel region, and a base line electrically connected to the channel region is formed on a sidewall at the other side of the pillar. A second doped region is formed in the upper part of the pillar.