Bonded 3D Memory Devices via Face-to-Face Semiconductor Interfaces
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Solution Overview
Problem
Current 3D NAND memory devices face challenges in achieving high yield and efficient carrier transport due to the complexity of aligning and bonding conductor/dielectric pairs, leading to undesirable coupling between adjacent memory cells and limited carrier transport rates, especially as devices scale vertically.
Innovation Solution
The proposed solution involves bonding semiconductor structures in a face-to-face manner, using conductive routings and bonding contacts to connect conductor layers without direct alignment at the bonding interface, allowing for flexible layout and reduced alignment precision, and integrating peripheral circuits into a separate semiconductor structure to facilitate easier fabrication and higher yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conductor/dielectric pairs are aligned and bonded directly at the bonding interface to form 3D NAND memory devices, then memory device integration is achieved, but alignment complexity and bonding difficulty increase significantly
Solution Approach 1:
The patent divides the 3D NAND memory device into multiple separate semiconductor structures (first semiconductor structure, second semiconductor structure, third semiconductor structure) that are bonded independently. Each structure contains specific conductor/dielectric pairs that are formed and processed separately before bonding, eliminating the need for complex direct alignment and bonding of all conductor/dielectric pairs at once. This segmentation reduces bonding process complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent introduces bonding interfaces as intermediary elements between semiconductor structures. At these bonding interfaces, conductor/dielectric pairs from different semiconductor structures are connected through intermediate bonding layers and bonding contacts, rather than requiring direct alignment and bonding. This intermediary approach simplifies the bonding process by providing tolerance for alignment variations and reducing the precision requirements.
2Reliability
If direct alignment and bonding of conductor/dielectric pairs is used, then memory device functionality is achieved, but yield decreases due to bonding complexity
Solution Approach 1:
By segmenting the device into multiple semiconductor structures that are bonded separately, the patent reduces the overall bonding complexity. Each bonding interface involves fewer conductor/dielectric pairs, making the bonding process more reliable and easier to control, thereby improving device yield.
Solution Approach 2:
The patent performs preliminary formation of conductor/dielectric pairs within each semiconductor structure before bonding. This preliminary action ensures that the conductor/dielectric pairs are already formed and positioned correctly within their respective structures, reducing the complexity and risk of errors during the bonding process itself, thus improving yield.
3Productivity
If conductor/dielectric pairs are directly bonded with high alignment precision, then carrier transport efficiency is maintained, but bonding process becomes overly complex
Solution Approach 1:
The patent uses bonding interfaces with intermediate bonding layers and bonding contacts as mediators to connect conductor/dielectric pairs from different semiconductor structures. This intermediary approach maintains electrical connectivity and carrier transport efficiency while allowing for less stringent alignment requirements, thereby reducing bonding process complexity.
Solution Approach 2:
The patent changes the bonding parameters by using bonding layers and bonding contacts with specific material properties and thicknesses that facilitate electrical connectivity without requiring ultra-precise alignment. This parameter change allows maintaining carrier transport efficiency while simplifying the bonding process.
4Ease of manufacture
If peripheral circuits are integrated into the same semiconductor structure as memory stacks, then device functionality is complete, but fabrication complexity and yield issues arise
Solution Approach 1:
The patent segments the device into separate semiconductor structures: some structures contain memory stacks while others contain peripheral circuits. This segmentation allows each structure to be fabricated and optimized independently, simplifying the manufacturing process and improving yield, while the bonding interfaces connect these structures to form the complete functional device.
Solution Approach 2:
The patent extracts peripheral circuits from the memory stack structure and places them in separate semiconductor structures. This extraction simplifies the fabrication of memory stacks by removing the complexity of integrating peripheral circuits, while the separated peripheral circuit structures can be fabricated using optimized processes for their specific functions.
Data Source
AI summary
Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory stack having a plurality of first conductor layers and a first bonding layer having a plurality of first word line bonding contacts conductively connected to the plurality of first conductor layers, respectively. A second semiconductor structure includes a second memory stack having a plurality of second conductor layers and a second bonding layer having a plurality of second word line bonding contacts conductively connected to the plurality of second conductor layers, respectively. The 3D memory device also includes a bonding interface between the first bonding layer and the second bonding layer, at which the first word line bonding contacts are in contact with the second word line bonding contacts.