Recessed Handle Wafer for Deep Implantation in SOI Flash Memory
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Solution Overview
Problem
In silicon-on-insulator (SOI) wafers, high-voltage implants for source/drain regions in flash memory cells are hindered by the insulating properties of the buried layer, preventing intended benefits such as deeper implantation to mitigate current crowding.
Innovation Solution
Forming source/drain regions in a recessed handle wafer region of the SOI substrate, allowing deeper implantation without dopants entering the buried insulator layer, and integrating these flash memory devices with CMOS or other logic circuits on a non-recessed device wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If high-voltage implants are performed in SOI wafers to deepen source/drain regions, then current crowding is reduced, but dopants enter the buried insulator layer preventing intended benefits
Solution Approach 1:
The patent divides the handle wafer into two distinct regions: a recessed region for flash memory devices and a non-recessed region for CMOS devices. This segmentation allows different implantation depths in different regions, enabling deep source/drain regions in the recessed area without dopants contaminating the buried insulator layer, thus resolving the contradiction between achieving deep implantation and maintaining implantation effectiveness.
Solution Approach 2:
The patent introduces a vertical dimension by creating a recess in the handle wafer. This recess allows the source/drain regions to be implanted deeper in the vertical direction within the recessed region while keeping the overall wafer structure intact. The recessed region acts as a localized deep-implantation zone that doesn't compromise the buried insulator layer, solving the contradiction between depth and effectiveness.
2Reliability
If deeper source/drain regions are formed to mitigate current crowding, then device performance improves, but dopant contamination of the buried insulator layer occurs
Solution Approach 1:
By segmenting the handle wafer into recessed and non-recessed regions, the patent confines dopant implantation to the recessed region only. This prevents dopant contamination of the buried insulator layer while still achieving the desired deep source/drain regions for improved device performance in flash memory cells.
Solution Approach 2:
The patent applies local quality by creating a recessed region with different geometric properties than the surrounding area. This localized structural modification allows deep implantation and high-performance flash memory devices to coexist with standard CMOS devices on the same wafer, enabling deep source/drain regions without causing harmful dopant contamination to the buried insulator layer.
3Productivity
If flash memory devices are integrated with CMOS devices on the same wafer, then manufacturing efficiency improves, but process compatibility challenges arise
Solution Approach 1:
The patent segments the wafer into distinct recessed and non-recessed regions, allowing flash memory and CMOS devices to be manufactured using different processes in their respective regions. This segmentation enables process compatibility by isolating the specialized deep-implantation process to the recessed region, while CMOS devices in the non-recessed region use standard processes, thus maintaining manufacturing efficiency without compromising process compatibility.
Solution Approach 2:
By creating a recessed region with localized structural differences, the patent enables different device types to coexist on the same wafer with different process requirements. The recessed region accommodates flash memory devices requiring deep implantation, while the non-recessed region supports standard CMOS processing, resolving the contradiction between manufacturing efficiency and process compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables deeper source/drain regions in flash memory cells on SOI wafers, reducing current crowding and facilitating integration with CMOS devices, beneficial for advanced process technologies.
Implementation Method 1
high-voltage implants for source/drain regions in flash memory cells are hindered by the insulating properties of the buried layer, preventing intended benefits such as deeper implantation
Data Source
AI summary
An integrated circuit arranged on a silicon-on-insulator (SOI) substrate region is provided. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.