3D NAND Memory Direct Source Contact via Hole Current Detection
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Solution Overview
Problem
In three-dimensional NAND memory devices, controlling the junction location at the bottom of the channel adjacent to the source select gate electrode is difficult due to the diffusion of phosphorus or arsenic ions, and the selective oxidation of the thick, heavily doped source select electrode leads to thicker oxide rings that are hard to strip, degrading the source select transistor performance.
Innovation Solution
A three-dimensional memory device employing a multi-gated p-n junction diode with a heavily doped p-type semiconductor direct strap contact structure, which eliminates the need for an n-type source region and uses hole current for read operations, reducing contact resistance and avoiding the issues associated with n-p-n transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick, heavily doped n-type source select gate electrode is used, then the source select transistor performance is improved, but selective oxidation leads to thicker oxide rings that are hard to strip, degrading device performance
Solution Approach 1:
The patent changes the doping type parameter from n-type to p-type for the source select gate electrode. This parameter change eliminates the selective oxidation issue that occurs with phosphorus or arsenic doped n-type material, while still achieving the desired source select transistor performance through hole current detection rather than electron current.
Solution Approach 2:
The patent inverts the conventional approach by using p-type doping instead of n-type doping for the source select gate electrode. This inversion fundamentally changes the electrical characteristics and eliminates the oxidation-related manufacturing difficulties associated with traditional n-type heavily doped source select gates.
2Reliability
If phosphorus or arsenic ions are diffused to form the source select gate electrode, then the source select transistor performance is improved, but junction location control at the bottom of the channel becomes difficult
Solution Approach 1:
The patent changes the doping type from n-type (phosphorus or arsenic) to p-type (boron or indium). This parameter change eliminates the diffusion control issues because p-type dopants have different diffusion characteristics and can be more precisely controlled during the formation of the source select gate electrode, achieving both good transistor performance and precise junction location control.
3Reliability
If an n-p-n transistor structure is used, then the source select transistor function is achieved, but contact resistance is increased and performance is degraded
Solution Approach 1:
The patent inverts the conventional n-p-n transistor structure by implementing a p-n-p structure with p-type source select gate electrode. This inversion reduces contact resistance because the p-type material has better ohmic contact characteristics with the adjacent p-type channel region, eliminating the need for complex n-type/doped interface engineering required in traditional n-p-n structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances channel conductance, reduces contact resistance, and improves the performance of the source select transistor by eliminating the need for a thick, heavily doped n-type source select gate electrode, thereby improving read and erase operations in three-dimensional NAND memory devices.
Implementation Method 1
uses hole current for read operations
Implementation Method 2
oxidizing surface portions of the undoped sacrificial semiconductor layer and the p-doped etch stop semiconductor layer, wherein a silicon oxide cap is formed from each physically exposed portion of the p-doped source semiconductor layer
Data Source
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AI summary
A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.