3D NAND Drain Side Select Transistor Voltage Compensation
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Solution Overview
Problem
Program disturb in 3D NAND memory devices occurs due to temperature dependence and location-specific issues, leading to unintended programming of unselected memory cells, which is not effectively addressed by existing technologies.
Innovation Solution
Adjusting the voltage applied to the gate terminal of drain side select transistors of unselected NAND strings based on both temperature and the location of the selected word line, using temperature compensation schemes to reduce program disturb by optimizing the control gate bias and minimizing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed voltage is applied to the gate terminal of drain side select transistors during programming, then the device structure remains simple, but program disturb occurs due to temperature dependence and location-specific issues
Solution Approach 1:
The patent applies dynamics by making the gate terminal voltage dynamic rather than fixed. The voltage is adjusted based on temperature conditions and the location of the selected word line, allowing the system to adapt to varying operational conditions and prevent program disturb effectively
Solution Approach 2:
The patent changes the voltage parameter based on temperature and word line location. By modifying the gate terminal voltage according to these parameters, the system compensates for temperature-dependent effects and location-specific program disturb issues, improving programming reliability
2Reliability
If temperature compensation is applied to all drain side select transistors, then program disturb is reduced, but the control complexity and energy consumption increase
Solution Approach 1:
The patent applies local quality by providing temperature compensation selectively based on the location of the selected word line. Different voltage adjustments are applied to different drain side select transistors depending on their position in the stack, rather than uniformly to all transistors, thus reducing energy consumption while maintaining reliability
3Reliability
If higher voltage is applied to compensate for program disturb, then unselected memory cells are protected, but leakage current increases in selected memory cells
Solution Approach 1:
The patent carefully adjusts the voltage parameter to achieve the minimum necessary compensation for program disturb. By optimizing the voltage based on temperature and location rather than applying excessive voltage uniformly, the system protects unselected cells while minimizing leakage current in selected cells
Data Source
Figure 1A
Figure 1B~1C
Figure 1D
AI summary
Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on the location of the word line that is selected for programming. In one aspect, the voltage that is applied to the control gates drain side select transistors of unselected NAND strings is adjusted during programming based on temperature. Greater temperature compensation may be applied when the selected word line is closer to the drain side select transistors.