Read-Only Memories TRIZ Cases

Segments NOR flash erase operations to fit within tight command windows, enabling use in HD-SIM cards.

A multi-level antifuse memory device uses polarity-dependent dielectric breakdown to create distinct resistance states.

Measuring combined current identifies programmed word lines, enabling dynamic erase-verify adjustments that prevent incomplete erasure and uncorrectable errors.

A floating-gate transistor array computes weighted sums by storing weights as threshold voltages and passing correlated currents.

Segmented strong and weak programming phases reduce junction leakage current while narrowing threshold voltage distribution range.

Negative wordline bias isolates unselected cells in virtual ground flash arrays to reduce bitline leakage current.

OTP controller prohibits lock status changes to unlock state, preventing external manipulation of critical security data stored in one-time programmable areas.

A regulator circuit uses a second bias circuit to pre-charge the feedback node near the reference voltage during a secondary non-operating state.

A semiconductor memory data transfer unit routes normal and parity bit line data through independent page buffers to a dedicated error correction bus.

A capacitorless memory device leverages impact ionization to store charge within a channel semiconductor layer for data retention.

Flash memory controller reads state register bits to detect operation completion, eliminating long rising times and reducing pin count in high capacity designs.

Applying negative voltage to word lines and coupling gates in split gate flash memory cells reduces required positive supply levels.

Heterogeneous multi-sensing circuit performs cell state detection under varied conditions to optimize read levels.

A NAND flash memory erase method restricts electron flow between selection transistors using specific voltage conditions.

A semiconductor memory apparatus shares a common global data line among multiple redundancy memory areas to manage data transmission across different banks.

Segmented soft programming with varying bias voltages reduces time and cost required to recover over-erased flash memory cells.

Compensates for temperature dependence and word line location by adjusting unselected string gate voltages, reducing program disturb in 3D NAND.

A memory controller estimates optimum read voltage using standard deviations and average threshold voltages of adjacent distributions.

A power supply switching circuitry manages voltage levels at memory device input nodes to maintain stable operation.

Concurrent defense code and error correction operations reduce read latency by reusing previous results to determine optimal voltages.

Control logic applies positive pre-boosting voltages to word lines in a memory array block.

Feedback detection terminates programming pulses early to reduce time and power while maintaining reliability.

Concurrent dual decoding paths bias all unselected word lines to reduce ramp-up time in non-volatile memory arrays.

A memory device uses a controller to activate a sense amplifier only during verification intervals for accurate data storage.

A semiconductor electrical fuse detection circuit uses a bias transistor to supply current for state reading.

A nonvolatile memory erasing method injects majority carriers through a forward bias between the source and body contact.

One Time Programmable switches secure data integrity by permanently disabling write access after verification, reducing hardware complexity.

Segmenting non-volatile memory into multiple sets with validation data prevents deterioration information loss during abnormal power termination.

Adjusting source and substrate voltages during flash memory testing stabilizes control gate potential.

Segmented saw-tooth programming waveforms reduce program noise in NAND flash while maintaining tight threshold voltage distributions.

Sequential multi-level programming of stacked word lines optimizes data storage efficiency in vertical NAND flash memory devices.

A test control block verifies nonvolatile memory circuits without programming cells, enabling post-packaging redundancy repair.

A word-line voltage regulating circuit uses a charge pump and comparator to dynamically adjust output voltages based on operational mode.

Write-assist latches amplify bit-line voltages to compensate for voltage drops along extended lines, restoring write margins and preventing data errors.

A memory device uses a nonvolatile block to store and transmit weak addresses for targeted refresh operations.

Multiplexing odd and even page bit lines to a dual dynamic data cache reduces read and program times while minimizing coupling between adjacent conductors.

Bus multiplexers segment flash channels to increase die count while maintaining signal integrity under high capacitance loads.

Regulating source and p-well voltages to positive DC levels enables current sensing, avoiding ground bounce delays that slow voltage sensing.

Dedicated bit line control voltage supply unit bypasses page buffer loading delays to accelerate ground voltage application for faster data erase cycles.

A semiconductor memory device structure manages floating body potentials through controlled gate voltages and impurity regions.

A 3D NAND memory structure uses segmented decks filled with dielectric material to isolate conductive layers and improve electrical connectivity.

Trim circuitry applies position-specific erase verify voltages to reduce cell stress and improve reliability during flash memory operations.

Controller reads adjacent cell data to adjust target cell thresholds, suppressing capacitive coupling interference and maintaining accurate read margins.

A flash memory sense circuit uses a boost driver to manage voltage levels at the sense node.

A nonvolatile memory device applies data-dependent precharge voltages to bit lines to enhance channel boosting efficiency.

Applying distinct voltages to selected and unselected top drain-side select gate transistors minimizes neighbor cross-coupling interference.

A semiconductor memory device applies distinct pass voltages to unselected word lines during program operations.

A data storing system adjusts read voltages using a pre-configured retry table to optimize retrieval accuracy.

Threshold circuitry transitions supply voltage to an intermediate level, reducing power consumption and complexity for reliable memory writes.

A post package repair circuit manages repair addresses using shared antifuse and register resources for dynamic mode selection.