Bus Multiplexer Grid for SSD Channel Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data storage devices face challenges in supporting high capacity configurations due to signal integrity issues and limited capacitance loads, which restrict the number of dies that can be accessed per channel, limiting transmission performance.
Innovation Solution
The implementation of bus multiplexers connected in series or parallel to flash interface modules, addressed by a chip enable command that identifies specific bus multiplexers and memory devices, allowing for increased dies per channel without compromising signal integrity or transmission performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple dies are connected in parallel to increase storage capacity per channel, then storage capacity is improved, but signal integrity deteriorates due to high capacitance loads
Solution Approach 1:
The invention segments the channel into multiple sub-channels using bus multiplexers. Each sub-channel connects to a subset of dies, reducing the capacitance load on any single sub-channel while maintaining the ability to access all dies through the multiplexed structure. This segmentation resolves the contradiction by allowing more dies per channel without compromising signal integrity.
Solution Approach 2:
Bus multiplexers are introduced as intermediary devices between the flash interface module and the dies. These multiplexers manage the connections and signal distribution, enabling multiple dies to be accessed while maintaining signal integrity through controlled signal routing and reduced capacitance exposure on individual signal paths.
2Quantity of substance
If the number of chip enable pins is increased to support more dies per FIM, then storage capacity is improved, but device complexity increases due to ASIC limitations
Solution Approach 1:
The bus multiplexer provides multi-functionality by serving multiple dies through a single or limited number of chip enable pins. Instead of requiring one pin per die, the multiplexer allows a small number of pins to control access to many dies by dynamically routing signals. This reduces ASIC complexity while enabling support for more dies per FIM.
Solution Approach 2:
The invention adds a time dimension to the address space by using sequential chip enable signals that activate different subsets of dies at different times. Instead of requiring all dies to be simultaneously addressable through parallel pins, the system uses time-multiplexed addressing, reducing the spatial complexity of the ASIC interface.
3Productivity
If transmission speed is increased to meet host performance requirements, then productivity is improved, but signal integrity deteriorates due to capacitance limitations
Solution Approach 1:
By segmenting the channel into sub-channels with fewer dies each, the capacitance load on any single transmission path is reduced. This allows transmission speed to be increased without the same level of signal integrity degradation that would occur with a parallel connection of many dies, as each sub-channel operates with lower total capacitance.
Data Source
AI summary
The present disclosure generally relates to a method and device for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected in series or in parallel to the FIM. The individual bus multiplexers can be addressed by a chip enable (CE) command that identifies the specific bus multiplexer as well as the specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without creating signal interference (SI) or limiting transmission performance.