Vertical NAND Flash Memory Programming Method for Interference Control
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Solution Overview
Problem
Current non-volatile memory devices face challenges in improving reliability and efficiency in programming operations, particularly in multi-level state programming across stacked memory cells connected to multiple word lines, which affects data storage capacity and accuracy.
Innovation Solution
A method for programming non-volatile memory devices involves sequentially programming memory cells of second to n−1-th word lines to a multi-level state and then programming the first word line to a single level state, with specific voltage control to ensure the maximum threshold voltage of the n−1-th word line is equal to or lower than that of the n-th word line, optimizing the program order and voltage levels to enhance reliability and data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed using conventional sequential methods, then programming simplicity is maintained, but reliability and data storage accuracy deteriorate due to interference between adjacent word lines
Solution Approach 1:
The patent segments the programming operation into distinct phases: first programming even-numbered word lines (0, 2, 4, ...) with even pass voltages, then programming odd-numbered word lines (1, 3, 5, ...) with odd pass voltages. This segmentation prevents interference between adjacent word lines by ensuring that when one word line is being programmed, its neighbors are held at non-programming voltage levels, thereby improving reliability without requiring fundamental changes to the memory architecture.
Solution Approach 2:
The patent applies preliminary actions by setting pass voltages on non-selected word lines before initiating programming on the target word line. Specifically, even-word lines are prepared with even pass voltages and odd-word lines with odd pass voltages in advance, creating a controlled voltage environment that prevents accidental programming or data corruption during the programming process, thus enhancing data storage accuracy.
2Quantity of substance
If multi-level programming is applied to all word lines simultaneously, then storage capacity increases, but programming errors increase due to voltage interference
Solution Approach 1:
The patent implements local quality by assigning different voltage characteristics to different word lines based on their parity. Even-numbered word lines receive even pass voltages (e.g., Vpass0, Vpass2, ...) while odd-numbered word lines receive odd pass voltages (e.g., Vpass1, Vpass3, ...). This localized voltage differentiation ensures that each word line can be programmed to multi-level states with appropriate voltage levels while preventing interference with adjacent word lines, thereby maintaining programming reliability even as storage capacity increases through multi-level programming.
3Manufacturing precision
If conventional programming voltage levels are used, then device operation is simple, but threshold voltage control precision deteriorates
Solution Approach 1:
The patent applies parameter changes by introducing a family of pass voltages with different magnitude levels corresponding to different word lines. Even pass voltages (Vpass0, Vpass2, Vpass4, ...) and odd pass voltages (Vpass1, Vpass3, Vpass5, ...) are defined with specific voltage levels that are tailored to the requirements of respective word lines. This parameter differentiation enables precise control of threshold voltages during programming operations, ensuring accurate multi-level state programming while maintaining systematic voltage control that does not overly complicate device operation.
Data Source
AI summary
A non-volatile memory device and a method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical direction over a substrate and connected to n word lines, wherein n is an integer greater than or equal to 3. The method includes programming memory cells of second to n−1-th word lines, from among first to n-th word lines that are sequentially disposed in the vertical direction over the substrate, to a multi-level state, wherein a multi-level program operation is sequentially performed from the second to n−1-th word lines in an order in which the word lines are disposed; and programming memory cells of the first word line to a single level state after the programming memory cells of the second to n−1-th word lines to a multi-level state.