Capacitor-less DRAM Noise Shielding via Ground Line Intermediary
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Solution Overview
Problem
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs causes noise, leading to erroneous reading or rewriting of storage data, making it difficult to commercially introduce such memory devices.
Innovation Solution
A semiconductor memory device with a structure comprising a semiconductor base material, impurity layers, gate insulating layers, and gate conductor layers, where the gate capacitance of one gate conductor layer is larger than the other, and voltages are controlled to perform write, erase, and read operations, with a reference voltage generating circuit and temperature-compensating circuit to manage noise and temperature effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor-less single-transistor DRAM structure is used, then device integration density is improved, but noise transmission to floating body causes erroneous reading or rewriting
Solution Approach 1:
A ground line is introduced as an intermediary element between the word line and the floating body. This ground line acts as a shield that intercepts and grounds the capacitive coupling noise before it can reach the floating body, thereby preventing erroneous reading or rewriting while maintaining the capacitor-less structure
Solution Approach 2:
The harmful capacitive coupling effect is extracted and redirected to the ground line instead of allowing it to directly affect the floating body. By providing an alternative path for the noise through the ground line, the harmful effect is removed from the data storage path
2Reliability
If ground line is added to reduce noise, then data integrity is improved, but device complexity increases
Solution Approach 1:
The ground line is designed with uniform properties and is integrated into the existing memory cell structure in a homogeneous manner. It uses the same fabrication processes and material layers as the other interconnect lines, avoiding the need for special complex structures or additional processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces noise transmission to the floating body, providing a sufficient margin between '1' and '0' potentials during writing and improving data integrity, enabling the commercial introduction of capacitor-less single-transistor DRAMs.
Implementation Method 1
Capacitive coupling between the word line and the floating body in capacitor-less single-transistor DRAMs causes noise
Implementation Method 2
accelerated electrons that flow from the source N+ layer 103 toward the drain N+ layer 104 collide with the Si lattice, and with kinetic energy lost at the time of collision, electron-positive hole pairs are generated (impact ionization phenomenon)
Data Source
AI summary
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit.