Semiconductor Memory Pass Voltage Control for Disturbance Suppression
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Solution Overview
Problem
Semiconductor memory devices face issues with program disturbance and read disturbance phenomena during operations, leading to increased operation time and power consumption.
Innovation Solution
The semiconductor memory device incorporates a peripheral circuit with a voltage generating unit and control logic that alternately performs program and verification operations, applying distinct pass voltages to word lines to suppress disturbances, with a second pass voltage being lower than a first pass voltage on unselected word lines adjacent to a selected word line, and continuously applying these voltages without discharge sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single pass voltage is applied to all unselected word lines during program operation, then the device structure is simple, but program disturbance occurs on unselected cell strings
Solution Approach 1:
The patent segments the unselected word lines into two groups: first unselected word lines (adjacent to selected word line) and second unselected word lines (non-adjacent). Different pass voltages are applied to each group, with the first group receiving a lower pass voltage and the second group receiving a higher pass voltage. This segmentation suppresses program disturbance on unselected cell strings while managing voltage control complexity through systematic grouping.
Solution Approach 2:
The patent applies different pass voltage levels to different spatial regions of unselected word lines based on their proximity to the selected word line. First unselected word lines adjacent to the selected word line receive a lower pass voltage to prevent program disturbance, while second unselected word lines farther away receive a higher pass voltage. This local quality approach optimizes disturbance suppression where it is most needed while reducing unnecessary voltage control elsewhere.
2Loss of energy
If discharge operations are performed between program and verification operations, then leakage current is reduced, but operation time increases
Solution Approach 1:
The patent maintains continuous application of pass voltages to unselected word lines throughout the program and verification operations without discharge sections. The first unselected word lines continue to receive the lower pass voltage and the second unselected word lines continue to receive the higher pass voltage throughout the entire program loop. This continuous voltage application eliminates discharge time while managing leakage current through the differentiated voltage levels, thereby reducing overall operation time.
3Reliability
If high pass voltage is applied to all unselected word lines, then channel potential is maintained, but power consumption increases
Solution Approach 1:
The patent applies different pass voltage levels to different groups of unselected word lines based on their spatial relationship to the selected word line. First unselected word lines adjacent to the selected word line receive a lower pass voltage since they are already protected by the program voltage on the selected word line. Second unselected word lines farther away receive a higher pass voltage to maintain channel potential. This differentiated approach maintains reliability while reducing overall power consumption compared to applying high voltage to all unselected word lines.
Data Source
AI summary
A semiconductor memory device may include a memory cell array including a plurality of cell strings, a peripheral circuit unit configured to perform a program loop for alternately performing a program operation and a verification operation on the memory cell array, and a control logic configured to control the peripheral circuit unit to perform the program loop, wherein, in performing the program loop, a second pass voltage applied to unselected word lines adjacent to a selected word line among a plurality of word lines coupled to the memory cell array is lower than a first pass voltage applied to remaining unselected word lines during the program operation, wherein a potential level of the first pass voltage is adjusted in accordance with an arrangement position of each of the plurality of word lines and the plurality of word lines are defined as a plurality of groups, and the first pass voltages applied to the plurality of groups, respectively, are different from one another.


