Non-Volatile Memory Bit Line Multiplexing for Parallel Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multilevel cell (MLC) non-volatile memory devices face performance bottlenecks due to increased read and program operations required as the number of data levels stored per cell increases, leading to longer read times and decreased memory performance.
Innovation Solution
Implementing an all bit line sense and program operation method that uses a current clamping circuit and multiplexing circuit to enable simultaneous read and program operations on all bit lines, along with a dynamic data cache for temporary storage and precharging, allowing for efficient data handling and reduced coupling between bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple read operations are performed to determine data levels in MLC cells, then data storage capacity per cell increases, but read time increases and performance decreases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank containing multiple pages of memory cells. Read operations are performed on entire pages simultaneously across multiple bit lines, rather than reading cells individually. This segmentation allows parallel read operations that reduce overall read time while maintaining multi-level data storage capacity.
Solution Approach 2:
The patent transitions from sequential cell-by-cell reading to parallel page-by-page reading across multiple bit lines. By operating on entire pages simultaneously in a single read operation, the system adds a dimensional aspect of parallelism that reduces read time without sacrificing the ability to store multiple data levels per cell.
2Manufacturing precision
If multiple pages are programmed separately in MLC devices, then programming precision is maintained, but programming time increases
Solution Approach 1:
Multiple separate programming operations on individual pages are merged into a single programming operation that simultaneously programs multiple pages across multiple bit lines. The control circuit enables this by coordinating word line and bit line selections to program entire pages in parallel, thereby maintaining programming precision while significantly increasing programming speed.
Solution Approach 2:
The programming operation continues without interruption by simultaneously programming multiple pages in parallel. Rather than completing one page programming before starting the next, the system maintains continuous useful action by overlapping programming operations across multiple pages, thus reducing total programming time while preserving precision through controlled voltage applications.
3Object-generated harmful factors
If bit lines are read sequentially, then coupling between bit lines is minimized, but read operation time increases
Solution Approach 1:
Before reading data from memory cells, the control circuit performs preliminary precharging of bit lines to a reference voltage level. This preliminary action ensures that bit lines are in a known state and reduces coupling effects during the actual read operation. By preparing bit lines in advance, the system minimizes interference between adjacent bit lines while enabling parallel reading operations.
4Ease of operation
If word lines are biased to turn on all cells except selected cell, then read operation simplicity is maintained, but read time increases for multi-level cells
Solution Approach 1:
The memory array is segmented into multiple pages, each with its own word line. Instead of biasing all word lines to read individual cells sequentially, the control circuit selects and biases only the specific word line corresponding to the desired page. This segmentation allows the system to maintain simple read operation logic while reducing read time by limiting the number of cells that need to be accessed simultaneously.
Data Source
AI summary
Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page bit lines to the dynamic data cache. The dynamic data cache comprises dual SDC, PDC, DDC1, and DDC2 circuits such that one set of circuits is coupled to the odd page bit lines and the other set of circuits is coupled to the even page bit lines.