Flash Memory Controller State Register Read Without Ready Busy Signal
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Solution Overview
Problem
Conventional flash memory control systems rely on the ready/busy (RB) signal for page read and write operations, which results in long rising times and increased pin count, complicating circuit layout and efficiency, especially in high-capacity flash memories.
Innovation Solution
A system and method that allow the flash memory controller to directly read the state register of the flash memory without using the RB signal, enabling the execution of page read and write operations by detecting the state of the state register and switching data accordingly, thereby reducing the need for the RB signal and improving operation speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ready/busy signal mechanism is used to control flash memory operations, then the flash memory can be properly controlled for page read operations, but the rising time becomes very long (25μs-50μs + 3μs) and the number of pins increases
Solution Approach 1:
The patent extracts and eliminates the ready/busy signal mechanism from the flash memory control system. By removing this external signal and using internal state register bits (specifically bit 6 of the status register) to indicate operational status, the system achieves the same control function without the associated long rising time and additional pin requirements.
Solution Approach 2:
The patent makes the status register multi-functional by using its bits to serve multiple purposes: indicating operational status, triggering state data switching, and controlling data output timing. This eliminates the need for separate dedicated control signals like ready/busy, thereby reducing pin count and simplifying the control interface.
2Reliability
If the ready/busy signal is used to indicate flash memory readiness, then proper operation control is achieved, but the number of pins increases and circuit layout becomes more complex
Solution Approach 1:
The patent makes the status register multi-functional by using its bits to serve multiple purposes: indicating operational status, triggering state data switching, and controlling data output timing. This eliminates the need for separate dedicated control signals like ready/busy, thereby reducing pin count and simplifying the control interface.
Solution Approach 2:
The patent merges the operational status indication function with the existing status register that is already part of the flash memory interface. By combining the ready/busy signal function into the existing status register bits, the system reduces the total number of pins and simplifies the control interface without sacrificing operational reliability.
3Difficulty of detecting and measuring
If the state bit is read continuously to determine readiness, then the flash memory can be monitored, but the previous contents of state register are displayed instead of correct memory data when REN is lowered
Solution Approach 1:
The patent performs preliminary action by checking the state bit (bit 6 of status register) before initiating the page read operation. This preliminary status check ensures that the flash memory is ready to receive the read command and will properly output data when REN is lowered, preventing the issue of displaying previous state register contents instead of correct memory data.
Solution Approach 2:
The patent uses feedback from the state bit to control the timing of the REN signal. By continuously monitoring the state bit and using it as feedback to determine when to issue the read command and when to enable data capture, the system ensures that memory data is correctly displayed on the IO bus rather than previous state register contents.
Data Source
AI summary
A system and method for controlling flash memory is provided for a flash memory controller to use a control interface to read the state register of at least a flash memory with received data for operation to detect whether the flash memory has already finished the operation on the received data without using an RB signal, and when the operation on the received data is to read, the controller can execute the state data switch so that the IO of flash memory can output correct flash memory data for read, or when the operation on the received data is to write, the controller can execute another data operation to save time and accelerate the data operation speed of the flash memory.