Write-Assist Latches for SRAM Bit-Line Voltage Restoration
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Solution Overview
Problem
The reduction in operation voltages of integrated circuits due to down-scaling leads to reduced read and write margins in SRAM cells, causing errors and slowing down write operations, as the voltage drop along bit-lines affects the reliability and speed of data storage in SRAM arrays.
Innovation Solution
The implementation of write-assist latches connected to bit-lines, controlled by assist-enable units and Y-decode signals, which amplify the bit-line voltages at the terminating ends to match the starting end voltages, ensuring reliable and faster write operations by restoring or increasing the voltage amplitudes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operation voltages are reduced due to down-scaling, then power consumption is reduced, but write margins are reduced causing errors and slower write operations
Solution Approach 1:
Write-assist latches are introduced as intermediary components between the write drivers and the SRAM cells. These latches receive the write signal from the write driver and amplify it to restore the bit-line voltage before the signal reaches the SRAM cell, thereby compensating for the voltage drop along the bit-line and improving write margin without increasing the operation voltage
Solution Approach 2:
The write-assist latches perform preliminary action by amplifying the write signal before it reaches the SRAM cell. This preliminary voltage restoration ensures that when the write signal arrives at the bit-line, it already has sufficient voltage amplitude to overcome the voltage drop and maintain adequate write margin, preventing errors before they can occur
2Quantity of substance
If bit-lines are made longer to increase array size, then storage capacity is increased, but voltage drop along bit-lines increases reducing write margin
Solution Approach 1:
Write-assist latches serve as intermediary voltage restoration devices positioned along the extended bit-lines. These latches compensate for the increased voltage drop caused by longer bit-lines by amplifying the write signal, thereby enabling longer bit-lines (and larger array size) while maintaining adequate write margin for reliable operation
3Speed
If write drivers are positioned closer to SRAM cells, then write speed is improved, but voltage amplification capability is reduced
Solution Approach 1:
Write-assist latches act as intermediary amplification stages positioned between the write drivers and SRAM cells. Even when write drivers are close to the cells, these intermediate latches provide the necessary voltage amplification to ensure sufficient write margin, thereby allowing close positioning (for speed) while maintaining amplification capability through the assist latch mechanism
Data Source
AI summary
A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.