Semiconductor Memory Redundancy Global Data Line Sharing
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Solution Overview
Problem
Existing semiconductor memory apparatuses face limitations in data processing speed due to the separate allocation of redundancy memory areas for each bank, which restricts the number of repairable failed cells and increases operation time when determining repair addresses, leading to reduced yield and increased operation speed.
Innovation Solution
Implementing a semiconductor memory apparatus with a common global data line shared among redundancy memory areas, allowing for integrated use of redundancy memory areas across multiple banks, and a controller that manages data transmission and selection of page buffers based on repair addresses, reducing the time required for programming, reading, and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy memory areas are separately allocated for each bank, then the repair operation can be performed within the same bank, but the number of repairable failed cells is limited and the operation time increases
Solution Approach 1:
The patent merges redundancy memory areas from multiple banks to share a common global data line, allowing any redundancy area to repair failed cells from any bank. This consolidation reduces the total number of redundancy areas needed and decreases operation time by eliminating separate repair pathways for each bank.
Solution Approach 2:
The patent creates a universal redundancy system where a single redundancy memory area can serve multiple banks simultaneously. The common global data line enables any redundancy area to be accessed by any bank that experiences failures, making the redundancy system multi-functional rather than bank-specific.
2Speed
If separate global data lines are used for each bank, then data transmission is dedicated and fast, but the number of required global data lines increases and redundancy operations become slower
Solution Approach 1:
The patent combines multiple bank-specific global data lines into a common global data line that serves multiple banks and redundancy areas. This reduces the total number of data lines required while maintaining efficient data transmission through shared infrastructure.
Solution Approach 2:
The patent implements dynamic allocation of the common global data line, where the data line is selectively assigned to different banks and redundancy areas based on operational needs. This dynamic sharing allows fast data transmission without requiring dedicated lines for each bank.
3Reliability
If more redundancy memory areas are provided for each bank, then more failed cells can be repaired, but the area occupied by redundancy memory increases
Solution Approach 1:
The patent merges redundancy memory areas across multiple banks into a shared pool, reducing the total area occupied by redundancy memory. Instead of each bank having its own dedicated redundancy areas, the system consolidates redundancy resources to serve all banks collectively.
Solution Approach 2:
The patent creates universally accessible redundancy memory areas that can repair failed cells from any bank. This multi-functional approach allows a smaller total redundancy area to provide equivalent or superior repair capability compared to bank-specific redundancy areas.
4Measurement precision
If repair addresses are determined by comparing with stored addresses, then accurate repair can be performed, but the time required for determination increases
Solution Approach 1:
The patent performs preliminary organization of repair address information in a structured format that enables faster comparison and matching. By pre-organizing the repair address data and establishing efficient comparison logic, the system reduces the time required for address determination while maintaining accurate matching.
Data Source
AI summary
A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.