Semiconductor Memory Data Transfer Unit for ECC Efficiency

The patent segments the bit line connections by creating separate first and second data buses, with the first data bus connected to bit lines for normal memory cells and the second data bus connected to bit lines for memory cells with defective bit lines. This segmentation allows defective bits to be isolated and repaired through bit line replacement without consuming ECC processing capacity, while ECC resources remain available for correcting aging-related errors in normal cells.

The patent introduces a bit line replacement mechanism as an intermediary solution between the memory array and ECC processing. By replacing defective bit lines with good bit lines from a spare pool, the system prevents defective bits from reaching the ECC processor, thereby preserving ECC processing capacity for its intended purpose of correcting storage errors rather than fabrication defects.

The patent implements dynamic data bus configuration where the width of the data bus varies depending on the operation mode. During normal operations, a first data bus with a certain width is used, while during ECC processing, a second data bus with a different width configuration is activated. This dynamic adjustment allows high-speed ECC processing without permanently increasing the column repair circuit area, as the bus width is adapted to the specific operational requirements.

The patent changes the parameter of data bus width based on operation mode. The data transfer unit configures the data bus to have a first width for normal data transfer and a second width for ECC processing. This parameter change enables the system to achieve high-speed ECC processing when needed while maintaining a compact column repair circuit structure for normal operations, thus avoiding permanent area increase.

The patent extracts defective bit lines from the main memory array and replaces them with good bit lines from a spare pool. By taking out defective bit lines before they can cause errors, the system reduces the need for extensive ECC redundancy data, thereby minimizing the additional chip area required for ECC processing while maintaining high data accuracy.

The patent prepares spare good bit lines in advance as a cushion against defective bit lines. During fabrication testing, defective bit lines are identified and replaced with pre-prepared good bit lines from the spare pool. This beforehand cushioning ensures that the memory array is protected against fabrication defects before normal operation begins, reducing the burden on ECC processing and minimizing the required chip area for error correction.