Detecting Programmed Word Lines in NAND Flash via Combined Current
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Solution Overview
Problem
In non-volatile memory devices, such as NAND flash memory, the existing erase-verify processes often result in incomplete erasure of programmed memory cells due to the upper tail of the erased-state threshold voltage distribution, leading to uncorrectable errors and reduced endurance, especially when the number of programmed word lines is unknown.
Innovation Solution
The system detects the number of programmed word lines by measuring combined currents at the source or bit lines, allowing for adjustment of the erase-verify test parameters based on this information to ensure uniform erasure, thereby preventing errors and extending memory device endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard erase-verify process is applied without detecting programmed word lines, then the erase operation can be performed quickly and simply, but incomplete erasure occurs due to the upper tail of the erased-state threshold voltage distribution, leading to uncorrectable errors
Solution Approach 1:
The system performs a detection operation before the erase-verify process to identify the number of programmed word lines. This preliminary action allows the subsequent erase-verify test parameters to be adjusted based on the detected state, ensuring complete erasure while maintaining process efficiency. The detection step is performed once before erasure, and the information is reused throughout the erase-verify process.
Solution Approach 2:
The erase-verify test parameters are dynamically adjusted based on the detected number of programmed word lines. Instead of using fixed parameters, the system modifies the verify threshold and test conditions according to the specific state of the memory block, optimizing the erasure process for each detected configuration and ensuring reliable erasure completion.
2Reliability
If the erase-verify test parameters are adjusted to ensure complete erasure of all possible states, then erasure reliability is improved, but the erase operation time increases and productivity decreases
Solution Approach 1:
By detecting the actual number of programmed word lines before erasure, the system avoids performing extended erase-verify tests that would be necessary for worst-case scenarios. The preliminary detection enables the system to tailor the erase-verify process to the actual state, completing erasure faster than generic conservative approaches while maintaining reliability.
Solution Approach 2:
The system changes the erase-verify test parameters based on the detected number of programmed word lines. When fewer programmed lines are detected, less stringent verify parameters can be used, reducing the number of verify cycles needed. This dynamic parameter adjustment optimizes the balance between erasure reliability and operation speed for each specific case.
3Reliability
If the number of programmed word lines is not detected, then the erase process is simpler to implement, but the threshold voltage distribution shows an upper tail that causes uncorrectable errors
Solution Approach 1:
The system replaces complex adaptive control mechanisms with a simpler detection-and-adjustment approach. Instead of implementing continuous monitoring and dynamic adjustment during erasure, the system performs a single detection of programmed word line count and uses this information to set appropriate verify parameters, simplifying the overall control architecture while achieving reliable erasure.
Solution Approach 2:
The detection of programmed word line count provides feedback that informs the subsequent erase-verify process. This feedback mechanism allows the system to adapt the verify parameters to the actual state of the memory block, ensuring that the erasure is complete without requiring overly complex real-time control systems. The feedback is used to select appropriate verify thresholds and test conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that memory cells are erased uniformly, reducing the likelihood of uncorrectable errors and enhancing the endurance of the memory device by accurately identifying and addressing the number of programmed word lines during the erase operation.
Implementation Method 1
measuring a combined current through a plurality of NAND strings
Data Source
AI summary
A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.