NOR Flash Erase Slicing for Tight Timing Constraints
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Solution Overview
Problem
Non-volatile memory technologies, such as NOR flash, face challenges with long erase times that exceed the tight command timings required in applications like HD-SIM cards, and power constraints limit background erase operations, making it difficult to implement these memories in systems with aggressive power management and tight timing constraints.
Innovation Solution
The method involves slicing long latency erase operations into smaller erase slices that can be integrated with write operations within a command window, allowing these slices to be executed without extending the overall command time, thereby enabling the use of NOR flash in applications with strict timing requirements by hiding or replacing long latency erase operations within shorter read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional NOR flash erase operations are used, then the memory can be erased completely, but the erase time exceeds the tight command timings required by applications like HD-SIM cards
Solution Approach 1:
The patent divides the long latency erase operation into multiple smaller erase slices that can be distributed across multiple command windows. Each erase slice is combined with a write operation, allowing the erase function to be segmented into manageable portions that fit within tight timing constraints while maintaining complete erase functionality.
Solution Approach 2:
The patent merges erase slices with write operations within the same command window. By combining these two operations into a single command structure, the system executes them concurrently, reducing the total time required and ensuring that erase operations complete within the strict timing requirements of applications like HD-SIM cards.
2Use of energy by moving object
If power is removed between flash commands for power management, then power consumption is reduced, but background erase operations cannot be performed
Solution Approach 1:
The patent initiates erase slices during active command windows when power is available, performing preliminary erase actions before power removal. By advancing the erase operation during powered-on periods, the system ensures erase progress is made before power management modes take effect, eliminating the need for continuous background erase operations that require sustained power.
Solution Approach 2:
The patent maintains continuous erase progress by distributing erase slices across multiple command windows rather than requiring a single continuous background erase operation. This approach ensures that useful erase action continues incrementally through multiple short-lived power windows, achieving complete erase functionality without requiring uninterrupted power supply for background operations.
3Speed
If NOR flash is used in applications with tight timing constraints, then the memory's fast read performance is utilized, but the long erase latency prevents its use in such applications
Solution Approach 1:
The patent segments the erase operation into multiple small slices that can be executed within tight command windows, making NOR flash adaptable to applications with strict timing requirements. This segmentation transforms the erase function from a blocking long-duration operation into a series of short operations that coexist with fast read and write operations, enabling NOR flash usage in HD-SIM card and similar applications.
Solution Approach 2:
The patent implements a dynamic erase slicing mechanism that adapts the number and size of erase slices based on the specific timing constraints and workload requirements of different applications. This dynamic approach allows the same NOR flash memory to be optimized for various applications with different timing requirements, enhancing its versatility and adaptability across different use cases.
Data Source
AI summary
A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period. A long latency erase command is sliced by a factor of n to provide a plurality of erase slices, each erase slice having the same time period. The method further includes executing n commands to the non-volatile memory, each command composed of the combination of one of the n write operations and one of the erase slices. The total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.