Pre-boosting Scheme for NAND Flash Program Disturb Reduction

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Solution Overview

Problem

In memory sub-systems, particularly non-volatile memory devices like NAND flash, programming disturbances occur due to residue electrons trapped in the poly-silicon channel, leading to incorrect data readouts and program disturb effects, which are exacerbated by high voltages during programming operations.

Innovation Solution

A pre-boosting scheme is implemented where control logic ramps down voltages to ground, applies positive pre-boosting voltages to selected and adjacent word lines, and a negative voltage to further word lines, creating a potential gradient to purge residue electrons from the source-side to the drain-side during the pre-boosting phase, ensuring they are cleared before subsequent programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high voltages are applied during programming operations, then programming speed and efficiency are improved, but program disturb effects are worsened due to residue electrons trapped in the poly-silicon channel

Engineering Contradiction:
Improveprogramming speedVSAvoidprogram disturb effects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies a preliminary boosting voltage to the bit line before the actual programming operation. This pre-boosting action creates a potential gradient that actively purges residue electrons from the channel before high programming voltages are applied, preventing program disturb effects while maintaining high programming speed. The boosting phase prepares the channel by removing trapped electrons that would otherwise cause disturbances during subsequent high-voltage programming operations.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If residue electrons are not purged from the channel, then device complexity is reduced, but program disturb effects worsen leading to incorrect data readouts

Engineering Contradiction:
Improvedevice complexityVSAvoiddata readout accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a preliminary boosting phase that actively purges residue electrons from the channel before programming operations. This pre-cleaning action ensures that when high voltages are subsequently applied, there are no residue electrons to cause program disturb effects or incorrect data readouts. The method maintains data readout accuracy without requiring additional hardware components, as the purging is achieved through carefully timed voltage sequences.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This significantly reduces program disturb effects by purging most residue electrons, preventing their injection into selected word lines during high program voltages, thereby improving program performance and reliability.

Implementation Method 1

a first positive pre-boosting voltage is applied to a first plurality of word lines... a second positive pre-boosting voltage is applied to a second plurality of word lines... a third pre-boosting voltage is applied to a third plurality of word lines

Methodology Applied
Scientific EffectPotential gradient: Electric Field

Data Source

PatentUS11670372B2Pre-boosting scheme during a program operation in a memory sub-system
Publication Date: 2023.06.06 MICRON TECHNOLOGY INC
  • US11670372B2 patent drawing
  • US11670372B2 patent drawing
  • US11670372B2 patent drawing

AI summary

Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.