Negative Wordline Bias for Flash Memory Leakage Reduction
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Solution Overview
Problem
Conventional flash memory devices with virtual ground architecture experience excessive bitline leakage current during programming, reading, and verification operations, leading to increased power consumption and potential errors in verification measurements due to parasitic leakage current, which worsens with the natural degradation of cells over program-erase cycles.
Innovation Solution
Implementing a method that involves establishing a negative gate bias voltage at unselected wordlines in flash memory systems with a virtual ground architecture to control and reduce bitline leakage current during programming, verification, and reading operations, thereby isolating unselected cells and minimizing leakage current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional virtual ground architecture is used for flash memory operations, then the memory device can perform programming, reading, and verification operations, but excessive bitline leakage current occurs leading to increased power consumption
Solution Approach 1:
The patent applies preliminary anti-action by establishing negative bias voltages on unselected wordlines before performing programming, reading, or verification operations. This pre-established negative bias creates a potential barrier that actively prevents leakage current from flowing through unselected cells, countering the harmful leakage effect before it can occur. The negative bias is applied in advance to all unselected wordlines, creating a protective potential landscape that redirects or blocks leakage paths.
2Measurement precision
If conventional virtual ground architecture is used, then memory operations can be performed, but parasitic leakage current causes errors in verification measurements
Solution Approach 1:
The negative bias applied to unselected wordlines creates a preliminary protective barrier that prevents parasitic leakage current from reaching the verification measurement path. By establishing this counteracting potential field before verification operations, the measurement circuitry is protected from leakage-induced errors, ensuring accurate verification current measurements.
Solution Approach 2:
The unselected wordlines with negative bias serve as an intermediary protective layer between the bitlines and the verification measurement circuitry. This intermediary structure with controlled negative potential acts as a barrier that blocks parasitic leakage current paths, preventing the leakage from directly affecting the verification measurements while allowing the selected cell to be properly accessed.
3Loss of energy
If negative gate bias voltage is applied to unselected wordlines, then bitline leakage current is reduced and power is conserved, but additional voltage control circuitry is required
Solution Approach 1:
The wordline control circuitry is designed to perform multiple functions: it selects specific wordlines for active operations while simultaneously applying negative bias to all unselected wordlines to prevent leakage. This multi-functional approach allows the same control structure to manage both selected and unselected wordlines, reducing the need for separate dedicated circuits for leakage control and improving overall system efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces bitline leakage current, conserving power and improving the accuracy of verification current measurements by isolating unselected cells and reducing parasitic leakage, thus enhancing the operational efficiency and reliability of flash memory devices, especially in low-power applications.
Implementation Method 1
establishing a negative gate bias voltage at unselected wordlines corresponding to unselected cells that share the first selectable bitline and the second selectable bitline
Data Source
AI summary
A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.