Semi-Circle Drain Side Select Gate Voltage Control
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Solution Overview
Problem
Semi-circle drain side select gate (SC-SGD) memory technology faces inefficiencies due to etching variations, leading to parasitic transistor leakage and threshold voltage distortion, affecting sensing operations and memory structure integrity.
Innovation Solution
Applying distinct voltages to unselected and selected top drain-side select gate transistors during memory operations, with the unselected voltage being intentionally different from the selected voltage, to minimize neighbor cross-coupling and interference effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If etching technology is used to create semi-circular memory holes and separate blocks into strings, then die size is reduced, but parasitic transistor leakage and threshold voltage distortion occur
Solution Approach 1:
The drain-side select gate is divided into multiple independent gates (first drain-side select gate and second drain-side select gate) positioned at different locations along the string. This segmentation allows independent voltage control of each gate, enabling selective suppression of parasitic leakage paths while maintaining the semi-circular memory hole structure for high density.
Solution Approach 2:
Different voltage levels are applied to different drain-side select gates based on their specific positions and functions. The first drain-side select gate receives a different voltage than the second drain-side select gate, creating local electrical conditions optimized for suppressing parasitic transistors in specific regions without affecting overall memory operation.
2Shape
If the metal shielding layer is removed during SC-SGD formation, then the semi-circular structure is achieved, but the SC-SGD becomes influenced by neighboring electric fields causing parasitic leakage
Solution Approach 1:
An intermediate shielding structure is formed between adjacent memory holes to block electric field interference from neighboring strings. This intermediate structure acts as a mediator that prevents the harmful electric fields from reaching the SC-SGD channels, thereby suppressing parasitic transistor leakage while preserving the semi-circular memory hole geometry.
3Ease of manufacture
If etching variation causes some dies to be cut down to SGD layer while others cut to dummy word lines, then manufacturing flexibility is maintained, but threshold voltage distortion occurs
Solution Approach 1:
The system employs dynamic voltage adjustment where different voltage levels are applied to different drain-side select gates based on their actual position and function. This dynamic control adapts to variations in etching depth, ensuring that regardless of whether a die is cut to the SGD layer or dummy word lines, the threshold voltage remains consistent through compensatory voltage application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current and stabilizes threshold voltage distributions, enhancing the accuracy of sensing operations and overall memory performance by mitigating the neighbor cross-coupling and interference effects.
Implementation Method 1
the SC-SGD can be influenced by a 'neighboring' electric field, causing a parasitic transistor to leak along the SC-SGD transistor
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is coupled to the word lines and bit lines and is configured to apply an unselected top voltage to unselected ones of the top drain-side select gate transistors during a memory operation. The control means is also configured to simultaneously apply a selected top voltage to selected ones top drain-side select gate transistors during the memory operation. The unselected top voltage is intentionally different electrically than the selected top voltage.