Multi-Level Antifuse Memory via Polarity-Dependent Breakdown
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Solution Overview
Problem
Existing one-time-programmable (OTP) memory technologies, such as antifuse bits, face challenges in achieving multi-level storage and reliable data retention due to limitations in dielectric breakdown mechanisms.
Innovation Solution
The development of a multi-level antifuse memory device using polarity-dependent dielectric breakdown in a metal-insulator-semiconductor (MIS) structure, allowing for three distinct resistance states by controlling the number and polarity of breakdown events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional antifuse bit with single dielectric breakdown is used, then simple binary storage is achieved, but multi-level storage capability is lost
Solution Approach 1:
The patent applies dynamics by making the dielectric breakdown process controllable and adjustable through voltage polarity switching. The system transitions from a static single-breakdown mechanism to a dynamic multi-breakdown mechanism where the number of breakdown events can be varied to create different resistance states, enabling multi-level storage while maintaining manageable device complexity through controlled variability.
Solution Approach 2:
The patent changes the parameter of voltage polarity applied to the dielectric layer. By switching between positive and negative voltage polarities, the system controls the number of breakdown events occurring in the dielectric material. This parameter change enables differentiation between multiple storage states (e.g., 0, 1, 2 breakdowns) without requiring fundamentally different device structures, thus achieving multi-level storage with controlled complexity.
2Speed
If higher voltage stress is applied to induce dielectric breakdown, then programming speed is improved, but data retention reliability deteriorates
Solution Approach 1:
The patent employs periodic action by applying voltage stress in discrete pulses with alternating polarities rather than continuous high voltage. The breakdown process occurs in periodic stages corresponding to each voltage pulse, allowing controlled progression through multiple breakdown events. This periodic application enables fast programming through cumulative breakdown while maintaining reliability by resetting the voltage polarity between stages, preventing runaway breakdown that would compromise data retention.
3Quantity of substance
If multiple breakdown events are used to create multi-level states, then storage density is improved, but read disturbance immunity worsens
Solution Approach 1:
The patent converts the potential harm of read disturbance into a beneficial differentiation mechanism. By designing the multi-level states based on odd/even numbers of breakdown events, the system ensures that normal read operations (which cause minimal breakdown) cannot accidentally transition between states. The harm of dielectric degradation is transformed into a robust state identification mechanism where the parity of breakdown events provides inherent immunity against read-induced errors, enabling high storage density with maintained read reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable and non-volatile multi-level storage with significant current window differences between states, enhancing data retention and read disturbance immunity.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Data Source
AI summary
A method for forming a memory device is provided. The method includes forming first and second metal-insulator-semiconductor (MIS) structures, wherein each of the first and second MIS structures comprises a semiconductor layer, an insulating layer over the semiconductor layer, and a metal electrode layer over the insulating layer; performing a first breakdown process to the first MIS structure; performing a second breakdown process to the second MIS structure; performing a first read operation by supplying a reading voltage pulse to the metal electrode layer of the first MIS structure and detecting a first read current flowing through the first MIS structure; and performing a second read operation by supplying the reading voltage pulse to the metal electrode layer of the second MIS structure and detecting a second read current flowing through the second MIS structure, wherein the second read current is greater than the first read current.