NAND Flash Memory Programming Method for Threshold Voltage Distribution Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing NAND-type flash memory programming methods face challenges in reducing threshold voltage distribution range while increasing bit line voltage, leading to increased junction leakage current and power consumption.
Innovation Solution
A non-volatile semiconductor memory device that applies a programming voltage incremented stepwise to the control gate of the target memory cell transistor, while maintaining a constant initial intermediate voltage to adjacent memory cell transistors, and further adjusts the intermediate voltage stepwise to suppress the expansion of the threshold voltage distribution range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the bit line voltage is increased to perform weak programming and narrow the threshold voltage distribution range, then the threshold voltage distribution range is narrowed, but the junction leakage current is increased and power consumption is increased
Solution Approach 1:
The programming operation is divided into two distinct phases: strong programming phase and weak programming phase. The strong programming phase uses normal bit line voltage to program most memory cells, while the weak programming phase uses increased bit line voltage only for cells that require threshold voltage adjustment. This segmentation allows the system to achieve narrow threshold voltage distribution without continuously applying high voltage that would cause excessive leakage current and power consumption.
Solution Approach 2:
Instead of applying weak programming (increased bit line voltage) to all memory cells, the invention applies it only partially to cells that require additional programming. The system performs strong programming first, then selectively applies weak programming only to cells whose threshold voltages fall outside the desired distribution range. This partial application of excessive action (higher voltage) achieves the desired precision without the full power consumption cost of universal weak programming.
2Manufacturing precision
If the bit line voltage is increased to perform weak programming, then the electric field between channel portion and floating gate is alleviated, but the junction leakage current is increased
Solution Approach 1:
The programming process is segmented into strong programming and weak programming phases. The weak programming phase with increased bit line voltage is applied only when necessary to adjust threshold voltage distribution, minimizing the duration and scope of high-voltage application. This reduces the cumulative effect of junction leakage current while still achieving the desired threshold voltage distribution precision.
Solution Approach 2:
The system performs strong programming first to quickly program the majority of memory cells, then skips directly to selective weak programming only for cells that need adjustment. This rushing through the majority of cells with normal voltage and only applying high voltage when absolutely necessary minimizes the time that junction leakage current flows, reducing its harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively narrows the threshold voltage distribution range without significantly increasing power consumption by reducing the electric field between the channel and floating gate, thereby enhancing programming efficiency.
Implementation Method 1
programming means for programming data to a programming target memory cell transistor among the plurality of memory cell transistors by applying a programming voltage to the control gate electrode of the programming target memory cell transistor
Data Source
AI summary
A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.