Semiconductor Memory Read Margin Adjustment via Adjacent Cell Coupling
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Solution Overview
Problem
NAND flash memory devices face challenges in accurately reading data due to capacitive coupling between adjacent cells, which affects the threshold levels and reduces read margins, especially during erasure operations.
Innovation Solution
The semiconductor memory device includes a memory cell array and a controller that reads data from adjacent cells to adjust the read conditions for the target cell, using multiple read levels to accurately determine the threshold voltage and suppress the influence of capacitive coupling, allowing for accurate data retrieval even when erasure levels change.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitive coupling between adjacent cells is considered during reading, then reading accuracy can be improved, but device complexity increases due to the need to read adjacent cells and adjust read conditions
Solution Approach 1:
The patent reads data from adjacent cells (WLn-1 and WLn+1) before reading the target cell (WLn) to determine the appropriate read condition. This preliminary action allows the system to anticipate and compensate for capacitive coupling effects on the target cell's threshold voltage, thereby improving reading accuracy without requiring complex real-time adjustment mechanisms
Solution Approach 2:
The patent uses the read data from adjacent cells as feedback to dynamically adjust the read condition (read level) for the target cell. By comparing the adjacent cell data with predetermined patterns, the system determines whether to apply a normal or adjusted read level, creating a feedback loop that compensates for capacitive coupling effects
2Reliability
If read conditions are adjusted based on adjacent cell data, then read margin can be maintained, but operation time increases due to additional reading steps
Solution Approach 1:
The patent implements a periodic reading sequence where adjacent cells (WLn-1 and WLn+1) are read alternately with the target cell (WLn). This structured periodic approach allows the system to efficiently gather necessary information from adjacent cells while maintaining a predictable and optimized timing sequence, minimizing the overall time penalty
Solution Approach 2:
By reading adjacent cells in advance before the target cell, the system prepares the necessary information for read condition adjustment beforehand. This preliminary action allows for more efficient timing during the actual target cell read operation, as the decision about which read level to use is already determined
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate reading of data from memory cells by adjusting read conditions based on adjacent cell data, effectively mitigating the impact of capacitive coupling and maintaining read margins, ensuring reliable data storage and retrieval.
Implementation Method 1
capacitive coupling between adjacent cells increases as elements are more micronized. Therefore, there is a problem that a threshold level of a cell which is written first changes when an adjacent cell is written
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are adjacent to each other, and the second and third memory cells are adjacent to each other. Data is stored into the memory cells in an order of the first, second, and third memory cells. When reading data from the second memory cells, the controller reads data from the first and third memory cells, and changes read conditions for the second memory cell in accordance with the read data.