Split Gate Flash Memory Using Complementary Voltage Supplies
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Solution Overview
Problem
Existing non-volatile memory cell devices require higher positive voltage supplies for read, program, and erase operations, leading to a less compact and space-inefficient layout, as they do not utilize negative voltages effectively.
Innovation Solution
Applying negative voltages to the word line and/or coupling gate during read, program, and erase operations for selected or unselected memory cells, allowing for a more compact and space-efficient layout by reducing the required positive voltage supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher positive voltage supplies are used for read, program, and erase operations, then the memory cell can achieve reliable operation, but the layout becomes less compact and space-inefficient
Solution Approach 1:
The patent changes the voltage parameter from single-polarity (positive only) to dual-polarity (positive and negative), allowing the memory cell to achieve reliable operation with lower magnitude voltages. By applying negative voltages to word lines and coupling gates during program and erase operations, the patent reduces the required positive voltage supply magnitude, enabling more compact layout while maintaining operation reliability
2Area of stationary object
If negative voltages are applied to word line and coupling gate, then the layout becomes more compact and space-efficient, but the device complexity increases due to complementary voltage supplies
Solution Approach 1:
The patent segments the voltage supply system into separate positive and negative voltage generators, with the negative voltage applied selectively to specific lines (word lines and coupling gates) only during program and erase operations. This segmented approach allows compact layout while managing complexity through targeted application rather than system-wide implementation
3Manufacturing precision
If higher positive voltage is used for program and erase operations, then programming accuracy and efficiency are maintained, but leakage and disturb effects increase
Solution Approach 1:
The patent changes the voltage parameter from high positive voltage to lower magnitude voltages with negative polarity applied to word lines and coupling gates during program and erase operations. This parameter change reduces leakage and disturb effects while maintaining programming accuracy through the complementary voltage approach, where negative voltages on control lines prevent unwanted charge injection into floating gates of unselected cells
Data Source
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AI summary
A non- volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.