NAND Flash Memory Erase Method Restricting Selection Transistor Electron Flow
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Solution Overview
Problem
In NAND type flash memories, the erase operation can adversely increase the threshold voltage of string and ground selection transistors due to electron flow, which affects memory cell performance.
Innovation Solution
A method is implemented where a first voltage is applied to the control gate of a programmable transistor, and a second voltage is applied to the substrate during an erase operation, with the first voltage being less than the second voltage, to restrict electron flow from the first selection transistor into the second selection transistor, preventing unwanted programming of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If an erase operation is performed on NAND type flash memory, then data in memory cells is erased, but electron flow adversely increases the threshold voltage of string and ground selection transistors
Solution Approach 1:
The selection transistor is divided into multiple segments: a first selection transistor connected to the bit line and a second selection transistor connected to the substrate. This segmentation allows independent voltage control of each segment, enabling the first selection transistor to be protected from electron flow during erase operations while still allowing the erase operation to proceed on memory cells.
Solution Approach 2:
Different voltage conditions are applied to different parts of the system during erase operations. The first selection transistor is maintained at a voltage that prevents electron flow (protecting it from threshold voltage increase), while the substrate and memory cells undergo the erase operation. This local differentiation of voltage conditions allows the erase function to work while protecting specific components.
2Productivity
If electrons flow during erase operation, then memory cells are erased, but threshold voltage of selection transistors increases adversely
Solution Approach 1:
Before the erase operation begins, the first selection transistor is placed in a protective state by applying appropriate voltages to prevent electron flow. This preliminary protective action ensures that when the erase operation subsequently occurs, the first selection transistor is already protected from threshold voltage increase, allowing both efficient erasure and precise voltage control.
Solution Approach 2:
The second selection transistor and substrate act as intermediaries that allow the erase operation to proceed while protecting the first selection transistor. Electrons flow through the substrate and second selection transistor during erasure, but the first selection transistor is shielded from this electron flow through voltage control, thus mediating between the erase function and the protection requirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively restricts electron flow during the erase operation, preventing an increase in threshold voltages of the transistors and enhancing the reliability and efficiency of the memory device.
Implementation Method 1
a first voltage is applied to a control gate of the first programmable transistor... to restrict flow of electrons from the first programmable transistor into the second programmable transistor
Data Source
AI summary
In one embodiment, an erase method for a memory including a memory array having at least first and second programmable transistors connected in series, includes restricting flow of electrons from the first programmable transistor into the second programmable transistor during an erase operation.