Dual Decoding Paths for Faster Unselected Word Line Ramp-Up
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Solution Overview
Problem
Non-volatile memory devices face challenges in achieving faster ramp-up times for memory operations, particularly in biasing all word lines to an unselected level, which hinders overall performance and efficiency.
Innovation Solution
The proposed solution involves using both decoding paths concurrently to bias all word lines of a block at the unselected level, optimizing memory structure and peripheral circuitry by separating them onto separate dies for individual technology optimization, and implementing advanced bonding techniques like Cu-to-Cu bonding and hybrid bonding to enhance connectivity and reduce fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single decoding path is used to bias all word lines to an unselected level, then device complexity is reduced, but ramp-up time increases and productivity decreases
Solution Approach 1:
The patent divides the decoding function into two separate decoding paths: a first decoding path for selecting specific word lines and a second decoding path for biasing all word lines to an unselected level. This segmentation allows each path to be optimized for its specific function, with the second path dedicated exclusively to rapid unselected level biasing, thereby reducing ramp-up time without overall system complexity increase.
Solution Approach 2:
The patent introduces a temporal dimension to the decoding process by operating the two decoding paths concurrently during memory operations. The first decoding path operates during the read/program phase while the second decoding path simultaneously biases unselected word lines, effectively adding a parallel time dimension that reduces overall ramp-up time without increasing spatial complexity.
2Device complexity
If memory structure and peripheral circuitry are integrated on the same die, then device complexity is reduced, but performance optimization is limited
Solution Approach 1:
The patent physically separates the memory structure from the peripheral circuitry onto different dies. The memory array is fabricated on a first die using memory-optimized processes while the peripheral circuitry (including the dual decoding paths) is fabricated on a second die using logic-optimized processes. This segmentation enables independent technology optimization for each component, improving overall memory operation efficiency.
Solution Approach 2:
The patent introduces bond pads as intermediary connection points between the memory die and peripheral die. These bond pads enable high-speed electrical connections while allowing each die to be optimized independently. The intermediary bonding interface facilitates efficient data and control signal transmission between the separated components without compromising performance.
3Ease of manufacture
If conventional bonding techniques are used for die attachment, then manufacturing is simpler, but connectivity performance and fabrication efficiency are reduced
Solution Approach 1:
The patent transitions from conventional wire bonding to direct Cu-to-Cu bonding and hybrid bonding techniques. This parameter change in the bonding method enables lower resistance connections, higher bandwidth, and reduced parasitic effects. The advanced bonding techniques allow for smaller bond pad sizes and higher density connections, improving fabrication efficiency and connectivity performance while remaining manufacturable with modern semiconductor processes.
Data Source
AI summary
In a non-volatile memory array such as a NAND memory, when a word line of a block is selected for a read or write, the selected word line is biased at one level through one decoding path, while the unselected word lines of a block are biased at a different level though another decoding path. For memory operations, such as leakage detection, in which all of the word lines are biased with the same level, such as an unselected voltage level, the selected word line decoding path is otherwise unused. To increase the speed with which word lines can be ramped-up, for operation that bias all of the word lines of a block at the unselected level, both of the decoding paths can be used concurrently to reduce ramp-up times.