Memory Refresh Control System for Weak Address Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face data retention issues due to leakage currents in MOS transistors, leading to errors in memory cells adjacent to frequently activated word lines, as existing refresh operations do not adequately account for varying data retention times across memory cells.
Innovation Solution
A memory device with a refresh control system that includes a nonvolatile memory block for storing weak addresses, a refresh counter, and a latch circuit to enable a weak refresh signal, allowing for simultaneous sensing and sequential transmission of weak addresses to manage memory cells with shorter data retention times, thereby performing a normal and weak refresh operation to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normal refresh operation is performed with a predetermined time interval, then data retention is maintained for most memory cells, but memory cells adjacent to frequently activated word lines experience data loss due to shorter retention times
Solution Approach 1:
The patent applies local quality by implementing different refresh strategies for different memory cell groups. Specifically, memory cells are divided into normal cells and weak cells (adjacent to frequently activated word lines), with each group receiving customized refresh operations tailored to their specific retention characteristics.
Solution Approach 2:
The patent segments the memory cell array into multiple groups based on their retention characteristics. A row address is divided into a normal address portion and a weak address portion, allowing independent refresh control for different cell groups with different retention requirements.
2Reliability
If refresh operations are performed frequently to maintain data in all memory cells, then data integrity is improved, but power consumption and operational overhead increase
Solution Approach 1:
The patent applies partial action by performing enhanced refresh operations only on weak memory cells that require it, rather than refreshing all memory cells with the same frequency. This reduces unnecessary refresh operations on normal cells, thereby lowering overall power consumption while maintaining data integrity where needed.
3Use of energy by moving object
If the refresh interval is extended to reduce refresh operations, then power consumption decreases, but data loss occurs in memory cells with shorter retention times
Solution Approach 1:
The patent uses preliminary action by pre-calculating and storing weak row addresses in a nonvolatile memory block before refresh operations. This allows the system to identify and prepare refresh targets in advance, enabling extended refresh intervals while ensuring that weak cells are refreshed at appropriate times to prevent data loss.
4Reliability
If a dual refresh strategy is implemented to address varying retention times, then data retention reliability improves, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a refresh control system that can handle both normal and weak refresh operations through a unified architecture. The same control block manages different refresh types by interpreting row addresses differently, reducing the need for entirely separate control circuits for each refresh mode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively manages memory cells with shorter data retention times, ensuring normal operation by implementing a dual refresh strategy that addresses the data retention challenges, reducing errors and maintaining data integrity across the memory device.
Implementation Method 1
a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses
Implementation Method 2
a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses
Implementation Method 3
a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation
Implementation Method 4
due to a coupling phenomenon occurring between the word line WLK and the word lines WLK−1 and WLK+1, influences may be exerted on the memory cells CELL_K−1 and CELL_K+1 coupled to the word lines WLK−1 and WLK+1
Implementation Method 5
an initial charge stored in a capacitor may eventually vanish due to a leakage current attributable to the PN coupling of a MOS transistor
Data Source
AI summary
A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.