Capacitorless DRAM Using Impact Ionization and Voltage Sequencing
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Solution Overview
Problem
The existing dynamic random access memory (DRAM) cells composed of one MOS transistor without a capacitor face operational challenges, including insufficient potential difference margin between '1' and '0' potentials during writing, leading to difficulties in commercialization and issues with gate-induced drain leakage current (GIDL current) causing data destruction.
Innovation Solution
A memory device using a semiconductor element is designed with a page composed of multiple memory cells arranged on a substrate, featuring a semiconductor base with impurity layers and multiple gate insulating and conductor layers. The device performs operations such as page write, erase, and read, with specific voltage control methods to manage hole groups and prevent GIDL current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a DRAM memory cell is composed of one MOS transistor without a capacitor to increase integration density, then the device complexity is reduced, but the potential difference margin between '1' and '0' potentials becomes insufficient leading to operational failures
Solution Approach 1:
The patent transitions from a planar 2D transistor structure to a 3D vertical transistor structure where the channel extends perpendicular to the substrate surface. This dimensional change increases the effective channel area without increasing the planar footprint, thereby improving the potential difference margin while maintaining high integration density.
Solution Approach 2:
The patent modifies key physical parameters of the transistor including increasing the channel length in the vertical direction, adjusting the gate voltage parameters, and optimizing the impurity concentration profiles. These parameter changes enhance the transistor's ability to maintain sufficient potential difference between logic states while operating without a capacitor.
2Speed
If high voltage is applied to the gate and bit line simultaneously to write data, then the writing speed is improved, but gate-induced drain leakage current is generated causing data destruction
Solution Approach 1:
The patent applies preliminary negative voltage to the bit line before applying high voltage to the gate during write operations. This preliminary action prevents the formation of high electric field conditions that would otherwise generate GIDL current, while still allowing fast data writing through controlled voltage sequencing.
Solution Approach 2:
The patent employs dynamic voltage control where the bit line voltage is adjusted in real-time based on the write operation phase. During the write pulse, the bit line voltage transitions from negative to ground level in coordination with the gate voltage, dynamically preventing GIDL current generation while maintaining writing speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances the retention characteristics of written data, improves the potential difference margin, and prevents data destruction due to GIDL current, thereby overcoming the limitations of existing capacitorless DRAM cells.
Implementation Method 1
an operation of controlling a voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer to form a hole group by impact ionization inside the channel semiconductor layer
Data Source
AI summary
A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.