3D NAND Memory Erase Operation Using Dummy Layer Biasing
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Solution Overview
Problem
In 3D NAND memory devices, the increased number of levels makes it difficult to effectively transport holes for erase operations, leading to uneven distribution and incomplete erasure of memory cells, despite the use of gate-induce-drain-leakage (GIDL) assisted body biasing.
Innovation Solution
The introduction of a novel erase operation scheme that applies high positive voltages to dummy memory layers between the source and drain of each memory string to generate band-to-band-tunneling current, injecting holes vertically and compensating for GIDL-generated holes, thereby improving hole distribution and erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory levels in 3D NAND memory devices is increased to improve memory density, then memory capacity is improved, but hole transport difficulty increases leading to uneven distribution and incomplete erasure
Solution Approach 1:
The patent segments the single long hole transport path into multiple shorter paths by introducing intermediate dummy memory layers. These dummy layers act as hole generation points that divide the transport distance, ensuring holes can reach all memory cells even in high-level devices where the direct path from source to drain becomes too long and inefficient.
Solution Approach 2:
Dummy memory layers serve as intermediary structures that facilitate hole transport. By applying positive bias to these intermediate layers, they generate holes through band-to-band tunneling that act as mediators to fill the gap between the source and the distant memory cells, compensating for the insufficient hole generation in traditional GIDL-assisted body biasing schemes.
2Device complexity
If traditional GIDL-assisted body biasing is used for erase operations, then the process is simple, but hole distribution becomes uneven in high-level devices
Solution Approach 1:
The patent applies different bias conditions to different regions of the memory device. By selectively applying positive bias only to intermediate dummy memory layers while maintaining ground potential on other word lines, the system creates localized hole generation zones that ensure uniform hole distribution throughout the vertical stack, addressing the specific problem of uneven distribution in high-level devices without complicating the overall erase operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and effectiveness of the erase operation in 3D NAND memory devices by ensuring more even hole distribution across memory cells, improving erase efficiency and completeness.
Implementation Method 1
applies high positive voltages to dummy memory layers between the source and drain of each memory string to generate band-to-band-tunneling current, injecting holes vertically
Data Source
AI summary
Implementations of the present disclosure provide 3D memory devices and methods for operating the 3D memory devices. In an example, a 3D memory device includes a plurality of memory layers and a dummy memory layer between the plurality of memory layers and a NAND memory string extending through the memory layers and the dummy memory layer. The NAND memory string includes a source, a drain, and a plurality of memory cells at intersections with the plurality of memory layers and between the source and the drain. The 3D memory device also includes a peripheral circuit configured to erase the plurality of memory cells. To erase the plurality of memory cells, the peripheral circuit includes a word line driving circuit configured to apply a positive bias voltage on the dummy memory layer.