3D NAND Memory Finger Layout With Top Selective Gate Cut
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, scaling becomes challenging and costly, and 3D memory devices are needed to increase density without increasing wafer size, while maintaining storage capacity.
Innovation Solution
A method for forming a 3D memory device involves creating an alternating dielectric stack, forming channel holes, and simultaneously constructing channel structures and a top selective gate cut structure, allowing for reduced wafer size without compromising storage capacity by rearranging channel structures and using a sacrificial wall for precise etching and filling processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nine rows of channel holes are arranged in a staggered manner in existing 3D NAND memory devices, then storage capacity is maintained, but wafer size becomes large
Solution Approach 1:
The patent transitions from a conventional planar arrangement of channel holes to a three-dimensional stacked architecture. By forming multiple layers of channel holes vertically (e.g., first set in lower dielectric layers, second set in upper dielectric layers), the design achieves higher storage capacity without increasing the lateral wafer area. This vertical stacking approach fundamentally changes the spatial dimensionality of the memory structure.
Solution Approach 2:
The memory device is divided into multiple independent memory fingers, where each finger contains a manageable number of channel holes (e.g., four rows per finger). This segmentation allows the overall storage capacity to be achieved through parallel arrays of smaller, more compact units rather than requiring a single large array, thereby reducing the required wafer size.
2Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then density increases, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of continuing to scale planar memory cells to smaller feature sizes, the patent transitions to a three-dimensional vertical stacking architecture. This approach achieves higher memory density by utilizing the vertical dimension rather than further reducing lateral dimensions, thereby avoiding the exponential increase in process complexity and cost associated with continued planar scaling.
3Area of stationary object
If wafer size is reduced without changing storage capacity, then device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory structure into multiple fingers with fewer channel holes per finger (e.g., four rows instead of nine). This segmentation reduces the lateral spacing requirements and allows for more relaxed etching precision requirements while maintaining overall storage capacity through vertical stacking and parallel finger arrays.
Solution Approach 2:
By moving to vertical stacking of channel holes in multiple dielectric layers, the patent reduces the lateral footprint of each memory finger. This dimensional transition allows smaller wafer sizes without proportionally increasing etching precision requirements, as the critical dimensions are managed in the vertical stacking process rather than lateral patterning.
Data Source
AI summary
A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, and a top selective gate cut structure having a laminated structure embedded in an upper portion of the alternating layer stack and extending along a lateral direction. The laminated structure of the top selective gate cut structure comprises a dielectric filling wall and a dummy channel and a dummy functional layer on both sides of the dielectric filling wall.