3D NAND Flash Memory Programming Disturb Mitigation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In 3D NAND flash memory devices, programming disturb occurs due to residual electrons trapped in dummy memory cells at the junction of stacked decks, affecting the programming of adjacent memory cells, as the bit line pre-charge becomes ineffective and threshold voltage shifts, leading to channel potential reduction.

Innovation Solution

Applying a negative pre-pulse signal to dummy word lines during the pre-charge period to repel electrons and enhance channel potential, thereby reducing programming disturb by using a control method that includes a bit line pre-pulse, selected and unselected word line signals, and a negative pre-pulse signal applied to dummy word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bit line pre-charge is applied to dummy memory cells during programming, then initial state is maintained, but threshold voltage becomes low and residual electrons are trapped causing programming disturb

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidprogramming disturb
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A negative pre-pulse signal is applied to the dummy memory cells before the actual programming operation to create a potential barrier that prevents residual electrons from being trapped. This preliminary counter-action occurs during the pre-charge period and establishes conditions that oppose the harmful electron trapping effect that would otherwise occur during subsequent programming operations.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The voltage parameter of the dummy word line is dynamically changed by applying a negative pre-pulse signal during the pre-charge period. This parameter change transforms the dummy memory cell threshold voltage to a higher state, preventing the low threshold voltage condition that causes residual electron trapping and programming disturb.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If dummy memory cells are arranged in initial state, then threshold voltage shift is avoided, but channel boost potential is reduced affecting adjacent memory cell programming

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidprogramming reliability
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The voltage parameter of dummy memory cells is dynamically adjusted by applying a negative pre-pulse signal during the pre-charge period. This creates a temporary parameter change that maintains threshold voltage stability while simultaneously providing the necessary channel boost potential for adjacent memory cell programming through the stacked deck structure.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The negative pre-pulse signal is applied in advance during the pre-charge period to prepare the dummy memory cells for the upcoming programming operation. This preliminary action establishes the appropriate electrical conditions that enable both threshold voltage stability and sufficient channel boost potential for reliable programming of adjacent memory cells.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The negative pre-pulse signal effectively reduces charge trap effects and increases channel potential, minimizing programming disturb and improving data storage reliability in 3D NAND flash memory devices.

Implementation Method 1

Applying a negative pre-pulse signal to dummy word lines during the pre-charge period to repel electrons and enhance channel potential

Methodology Applied
Scientific EffectElectron repulsion: Ion Repulsion/Attraction

Data Source

PatentEP3881322B1Non-volatile memory device and control method
Publication Date: 2023.12.06 YANGTZE MEMORY TECH CO LTD
  • EP3881322B1 patent drawingFigure 1
  • EP3881322B1 patent drawingFigure 2
  • EP3881322B1 patent drawingFigure 3

AI summary

A non-volatile memory device is disclosed. The non-volatile memory device includes a memory array, a plurality of word lines, a plurality of dummy word lines, a first control circuit and a second control circuit. The plurality of word lines are connected to a plurality of top memory cells and bottom memory cells of a memory string of the memory array. The plurality of dummy word lines are connected to a plurality of dummy memory cells connected between the plurality of top memory cells and bottom memory cells. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a selected word line signal to a selected word line, apply an unselected word line signal to unselected word lines and apply a negative pre-pulse signal to the plurality of dummy word lines.