Read-Only Memories TRIZ Cases

Subdividing the programming window into time intervals reduces peak current demand, enabling smaller charge-pumping circuits and improving robustness.

A memory controller manages differential power consumption values to enable concurrent command execution across multiple memory chips.

Dynamic switching between low-power standby and high-accuracy active detection circuits prevents data corruption during power-off events.

A serial flash memory controller manages concurrent read and write operations across independent array planes.

A multi-pass memory programming method identifies noisy cells via additional verify tests to suppress read noise.

Adjusts verification voltage per group to compensate for sensing parasitic resistance, ensuring equal operating windows and uniform programming.

A controller adjusts operation voltage of select transistors to maintain semiconductor memory device reliability.

A state confidence error correction module encodes logical states using multiple sense operations to improve data accuracy in non-volatile memory arrays.

Staged pre-charging of the sense node and bit line suppresses peak current noise during reading operations, preventing power voltage drops in low-power devices.

Segmented drivers with independent bias voltages minimize erase disturbance and leakage current.

Independent gate structures apply shielding voltages to adjacent word lines in FinFET memory arrays.

A fuse link programming cell array uses mode control transistors to enable redundancy correction for efuse units.

Segmented source lines with selector switches isolate unselected memory cells, suppressing leakage current and reducing bias line complexity.

A nonvolatile memory reading circuit adjusts bit line precharge based on adjacent cell states to maintain threshold voltage levels.

An oscillator-driven accumulator determines read voltage offsets to resolve data bus congestion and latency penalties in memory sub-systems.

A sense amplifier circuit uses a step voltage line and reference-voltage generator to detect read signal voltages.

Segmenting non-selected pages into programmed and non-programmed groups allows applying different pass voltages to stabilize threshold voltage distributions.

A circuit generates interleaver addresses by dividing data blocks into windows and calculating modulo values.

Load signals generated from MSB and LSB logic levels determine programming permissions, reducing the number of operations required to store data states.

A memory access interface device adjusts signal phase and duty cycle to synchronize data transfer across operating modes.

An on-die controller adapts programming voltage to prevent over-programming and threshold voltage shifts in non-volatile memory arrays.

Segmented converters with distance-based switching resolve read access reliability issues caused by voltage source distance variations.

A fuse programming circuit stabilizes current using a bypass resistor, preventing transient errors during semiconductor manufacturing.

A memory controller randomizes data using a seed offset within restricted page regions to stabilize storage.

A memory controller classifies non-volatile memory cells into groups and applies optimized read voltages to each group.

A processing unit transforms electrical variables into the time domain to detect memory cell states via threshold comparison.

Segmented EEPROM memory architecture reduces parasitic capacitance and crosstalk, enhancing read access times while lowering electrical consumption.

A semiconductor memory device applies distinct voltages to second select lines to generate gate-induced drain leakage current during erase operations.

Serial data paths reduce tester channel requirements, enabling simultaneous testing of multiple dies while maintaining 8-bit data integrity.

A sudden power off detection circuit uses a sensing cell and dual drivers to identify abrupt power loss events within nonvolatile memory arrays.

Selective pre-programming narrows threshold voltage distribution while avoiding the time penalty of programming all erased cells.

A memory read circuit calculates current-to-voltage slope characteristics from two sensing processes to determine data storage states.

Dynamic pulse timing reduces program disturb and boosts throughput in charge trapping NAND memory.

Modifying read voltages in multi-level non-volatile memory cells to discriminate between stored states.

A storage controller measures nonvolatile memory temperature to determine optimal rewriting intervals for data placement.

A memory driver circuit maintains equal programming voltages during transient periods to stabilize electrical conductivity.

Enable Control circuit activates nearest charge pumps first via staggered sequences, reducing noise and peak current while preventing voltage delivery delays.

A page buffer with main and sub-data latches selectively flips the main latch based on bit line voltage levels to map threshold voltages.

Lifetime markers track flash memory wear via read disturb and erase pulses to correct environmental drift in remaining life estimates.

A semiconductor memory device uses a conversion circuit to transform 4-bit data into 2-bit data during write operations.

Source-side column select architecture reduces background leakage and GIDL stress by moving selection transistors from the drain side to the source side.

A memory programming method adjusts pass bias voltage on dummy word lines based on selected word line groups.

A negative pre-pulse signal applied to dummy word lines during the pre-charge period repels trapped electrons and increases channel potential.

Averaging multiple current mirrors stabilizes programming current for advanced nanometer flash memory cells, reducing variability from 62% to 7.3%.

Moving bitline precharge and column selection to the preactive command shortens the activate phase duration, reducing overall read access time.

Asynchronous precharging minimizes supply voltage noise and average consumption during dual work mode sensing operations.

A non-volatile memory controller performs partial block erase verification on unprogrammed regions to mitigate read disturbance effects.

A page buffer circuit uses charge sharing between a storage node and a sensing node to refresh data in a dynamic latch.

A sensing circuit uses a switch group to adjust conduction paths for accurate non-volatile memory testing.