Nonvolatile Memory Read Access Time Reduction
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Solution Overview
Problem
Nonvolatile memory devices, such as phase-change memory, have slower read access times compared to volatile memory, making them less competitive in applications where speed is crucial, despite their ability to retain data.
Innovation Solution
Modifying the standard read access process by rearranging operations, specifically moving the bitline precharge and column selection from the activate command to the preactive command, as per the LPDDR2 standard, to reduce memory access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the standard read access process is used with sequential operations in activate command, then the process follows conventional timing, but the read access time is longer
Solution Approach 1:
The patent applies preliminary action by moving the bitline precharge and column selection operations from the activate command to the preactive command. This allows these operations to be performed in advance during the preactive phase, so that when the activate command is executed, the bitlines are already precharged and column selection is already done, thereby reducing the overall read access time despite extending the preactive phase duration.
2Productivity
If operations are rearranged to shorten activate phase, then the overall read access time is reduced, but the preactive phase is lengthened
Solution Approach 1:
The patent applies preliminary action by moving the bitline precharge and column selection operations from the activate command to the preactive command. This allows these operations to be performed in advance during the preactive phase, so that when the activate command is executed, the bitlines are already precharged and column selection is already done, thereby reducing the overall read access time despite extending the preactive phase duration.
Solution Approach 2:
The patent applies segmentation by dividing the read access process into distinct phases (preactive and activate) and redistributing operations between them. Specifically, it segments the bitline precharge and column selection operations from the activate command and places them in the preactive command, creating a more efficient temporal distribution of tasks that reduces critical path delays.
Data Source
AI summary
A method may comprise executing a read operation to access a memory array by performing a preactive command to include a row-address-write operation and a bitline precharge and column selection operation and performing an activate command including a column-address-write operation and a row-decode-selection operation.


