Sense Amplifier Circuit for Semiconductor Storage Device
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Solution Overview
Problem
As semiconductor storage devices are downscaled, variations in memory element characteristics and transistor threshold voltages lead to erroneous data read due to variations in pair transistors within sense amplifier circuits, necessitating a circuit configuration that prevents erroneous reads.
Innovation Solution
A semiconductor storage device configuration that includes a memory cell array with a sense amplifier circuit using a step voltage line and a reference-voltage generator, where the sense amplifier circuit detects read signal voltages and reference voltages by comparing them using operational amplifiers and latch circuits to accurately differentiate between data '0' and '1' without being affected by transistor variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor storage devices are downscaled to increase storage capacities, then storage capacity is improved, but variations in transistor threshold voltages and memory element characteristics increase causing erroneous data read
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the read operation. This pre-charge voltage is set to be higher than the threshold voltage of the read transistor, ensuring that the transistor is turned on before the actual read signal is applied. This preliminary voltage preparation compensates for threshold voltage variations in downscaled transistors, preventing erroneous data read while maintaining high storage capacity.
2Quantity of substance
If downscaling is progressed to increase storage capacities, then storage capacity is improved, but variations in pair transistor characteristics cause erroneous read
Solution Approach 1:
The patent introduces an intermediary mechanism by using a sense amplifier circuit that includes a read transistor and a pair of transistors configured as a differential amplifier. This intermediary circuit amplifies the small voltage differences resulting from memory cell readings, making the detection immune to variations in individual transistor characteristics. The differential configuration cancels out common-mode variations, enabling accurate data detection despite downscaling-induced transistor variations.
3Device complexity
If conventional sense amplifier circuits are used with downscaled transistors, then device complexity is maintained, but erroneous reads occur due to threshold voltage variations
Solution Approach 1:
The patent applies parameter changes by modifying the voltage parameters in the sense amplifier circuit. Specifically, it uses a pre-charge voltage that is higher than the threshold voltage of the read transistor, and adjusts the bit line voltage to optimize the operating point. These parameter adjustments ensure that the sense amplifier reliably detects data even when transistor threshold voltages vary due to downscaling, improving read operation reliability without significantly increasing circuit complexity.
Data Source
AI summary
A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. First bit lines transmit read signal voltages from the memory cells. A gate of a first transistor is connected to the first bit lines. A second bit line is connected to one of a drain and a source of the first transistor. A step voltage line is connected to the other one of the drain and the source of the first transistor to apply a step voltage changing in a stepwise manner to the first transistor at a time of reading. A reference-voltage generator generates a reference voltage. A sense part is connected to the second bit line to receive the read signal voltages and the reference voltage.