MLC Flash Memory Load Signal Programming Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional multi-level cell (MLC) flash memory devices require a higher number of operations to program data, increasing programming time due to the need to determine specific states based on read MSB and LSB data.

Innovation Solution

A memory device and method that includes buffers for receiving MSB and LSB data, generating load signals based on logic levels to control programming permissions, reducing the number of operations required for programming by using load signals to determine programming states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional MLC flash memory programming operations are used to determine specific states based on read MSB and LSB data, then data state determination is achieved, but programming time increases due to higher number of operations

Engineering Contradiction:
Improvedata state determination accuracyVSAvoidprogramming time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-determining programming permissions based on the relationship between MSB and LSB data before executing the programming operation. The control circuit generates programming permission signals in advance by comparing MSB and LSB values, allowing the system to prepare the programming state beforehand. This reduces the number of operations needed during the actual programming phase, thereby decreasing programming time while maintaining accurate data state determination.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If multiple read operations are performed to determine memory cell states, then accurate state identification is achieved, but the number of operations increases

Engineering Contradiction:
Improvestate identification accuracyVSAvoidprogramming efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent merges the functions of reading and determining programming permissions into a single integrated process. The control circuit simultaneously performs read operations on both MSB and LSB data and immediately uses this information to generate programming permission signals. By combining these operations rather than performing them separately, the system reduces the total number of operations required while maintaining accurate state identification, thereby improving programming efficiency.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If conventional programming operations are used without load signals, then programming flexibility is maintained, but programming time increases due to more operations

Engineering Contradiction:
Improveprogramming flexibilityVSAvoidprogramming time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent introduces programming permission signals as an intermediary mechanism between data reading and programming execution. These load signals act as mediators that automatically determine whether programming should proceed based on the relationship between MSB and LSB data. This intermediary layer maintains programming flexibility by allowing conditional programming decisions while reducing the number of operations needed, as the permission signals automatically handle the determination logic without requiring additional manual operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7529127B2Memory device and method thereof
Publication Date: 2009.05.05 SAMSUNG ELECTRONICS CO LTD
  • US7529127B2 patent drawing
  • US7529127B2 patent drawing
  • US7529127B2 patent drawing

AI summary

A memory device and method thereof are provided. The memory device may comprise a first buffer for receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell; a second buffer for loading LSB data stored in the memory cell; and a data loader for generating at least one load signal based upon logic levels of the received MSB data in the first buffer and the loaded LSB data in the second buffer, the at least one load signal being configured to control programming permissions for the memory cell.