Memory Read Circuit I-V Slope Sensing for Retention Loss

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory structures experience significant programming window retention loss over time and with increased operating temperatures, leading to a higher likelihood of read failures due to the reduction in the range between the current levels representing different logic values.

Innovation Solution

A memory structure with a read circuit that captures and processes the results of two consecutive single-ended current sensing processes using different input voltages to calculate and compare the current-to-voltage slope characteristics of memory cells, allowing for the detection of data storage states based on mutual conductance or conductance, thereby reducing programming window retention loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If single-ended sensing based on a single current-to-voltage characteristic is used, then the device complexity is reduced, but the programming window retention loss increases over time and temperature

Engineering Contradiction:
Improvesensing circuit complexityVSAvoidprogramming window retention
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The sensing operation is segmented into two separate single-ended sensing processes performed at different input voltage levels. Each process captures a portion of the I-V characteristic, and the results are combined to form a complete picture of the memory cell state. This segmentation allows accurate determination of the programming window without requiring a complex differential sensing circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The approach transitions from measuring a single current-to-voltage point to measuring two points and analyzing the slope between them. By adding the dimensional aspect of voltage variation and calculating the derivative (slope), the system can accurately determine memory cell states even as the absolute current values drift with temperature and time.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If the programming window range is reduced over time and temperature, then the memory cell operates under normal aging conditions, but the likelihood of read failures increases

Engineering Contradiction:
Improveoperating temperatureVSAvoidread failure rate
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The system uses feedback from two separate measurements to dynamically determine the memory cell state. By comparing the results from two sensing operations at different voltage levels and calculating the slope, the system can adapt to changes in the programming window caused by temperature and aging, thereby maintaining high read reliability under varying operating conditions.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If two consecutive single-ended sensing processes with different input voltages are performed, then the current-to-voltage slope characteristic can be calculated, but the measurement time increases

Engineering Contradiction:
Improvedata storage state detection accuracyVSAvoidsensing operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The sensing operation is performed in two periodic stages: first sensing at one voltage level, then sensing at a different voltage level. This periodic approach allows accurate slope calculation for reliable state detection while maintaining a structured timing sequence that minimizes total measurement time compared to continuous monitoring approaches.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11380373B1Memory with read circuit for current-to-voltage slope characteristic-based sensing and method
Publication Date: 2022.07.05 GLOBALFOUNDRIES US INC
  • US11380373B1 patent drawing
  • US11380373B1 patent drawing
  • US11380373B1 patent drawing

AI summary

Disclosed is a memory structure including an array of memory cells and a read circuit. The read circuit includes two registers configured to capture and store two different digital-to-analog converter (DAC) codes, which correspond to two different reference currents that approximate two different output currents generated on a bitline during consecutive single-ended current sensing processes directed to the same selected memory cell but using different input voltages. Optionally, the read circuit can also include a current-voltage (I-V) slope calculator, which uses the two different DAC codes to calculate an I-V slope characteristic of the selected memory cell, and a bit generator, which performs a comparison of the I-V slope characteristic and a reference I-V slope characteristic and based on results of the comparison, generates and outputs a bit with a logic value that represents the data storage state of the selected memory cell. Also disclosed is an associated method.