Flash Memory Word Line Driver Segmentation
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Solution Overview
Problem
Existing word line driver designs for flash memory devices consume significant circuit space as they cannot shrink proportionately with reducing cell sizes, leading to increased area consumption and inefficiencies in biasing conditions, particularly during erase operations.
Innovation Solution
A two-transistor word line driver design is implemented, where each local word line is coupled to a main word line through a PMOS and NMOS transistor, allowing for reduced driver size and efficient biasing to minimize erase disturbance and leakage current, thereby optimizing circuit area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional word line driver designs are used, then biasing functionality is maintained, but circuit space consumption increases and does not scale with cell size reduction
Solution Approach 1:
The word line driver is segmented into two separate transistors: a first transistor for generating the word line voltage and a second transistor for coupling the word line to the main word line. This segmentation allows each transistor to be optimized independently, reducing the overall driver area while maintaining functionality.
Solution Approach 2:
The patent applies different bias voltages to the first and second transistors during erase operations. The first transistor receives a first bias voltage and the second transistor receives a second bias voltage, allowing optimization of each transistor's operating parameters to minimize area while maintaining erase performance.
2Reliability
If traditional biasing schemes are used during erase operations, then erase functionality is maintained, but erase disturbance and leakage current increase
Solution Approach 1:
Different bias voltages are applied to different parts of the driver circuit during erase operations. The first transistor receives a first bias voltage while the second transistor receives a second bias voltage, allowing each component to be optimized for its specific function and minimizing harmful effects like leakage and disturbance.
Solution Approach 2:
The patent applies reverse bias voltages to the transistors during erase operations to prevent unwanted charge injection and leakage. By pre-biasing the transistors in opposite directions, the circuit proactively counteracts potential harmful effects before they occur.
3Ease of operation
If more transistors are used in the word line driver, then biasing control is improved, but device area and complexity increase
Solution Approach 1:
The driver is divided into exactly two transistors with distinct functions: voltage generation and coupling. This minimal segmentation provides sufficient biasing control for all operations (read, program, erase) without adding unnecessary complexity or area.
Solution Approach 2:
The two-transistor driver structure is designed to handle multiple operations (read, program, erase) using the same components. By making the driver universal across different operations, the patent avoids adding extra transistors for specialized functions, thereby minimizing area while maintaining ease of operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-transistor design reduces the size of word line drivers, saving circuit space and improving operational efficiency by minimizing erase disturbance and leakage current, while maintaining effective biasing for read, program, and erase operations.
Implementation Method 1
each local word line is coupled to a main word line through a PMOS and NMOS transistor
Data Source
AI summary
A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.