Source-Side Column Select for Flash Memory Leakage
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Solution Overview
Problem
Background leakage and gate-induced-drain-leakage (GIDL) stress are significant issues in hot-carrier-injection programming schemes for flash memory devices and flash-based FPGA devices due to the use of high-voltage transistors at the drain side, requiring large-area well boundaries and sector-based column select schemes.
Innovation Solution
Implementing a source-side column select architecture using medium-voltage transistors, where odd and even-select transistors are coupled to common drain lines, allowing for smaller segmentation and reduced leakage by controlling gate voltages on select transistors, thereby minimizing GIDL disturb and eliminating the need for expensive well boundary design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a drain-side column-select transistor is used for programming, then hot-carrier-injection programming can be achieved, but background leakage and GIDL stress increase significantly
Solution Approach 1:
The patent inverts the conventional placement of the column-select transistor from the drain side to the source side of the memory transistor. This inversion changes the voltage conditions during programming, allowing the use of lower voltages that reduce GIDL stress and background leakage while maintaining hot-carrier-injection programming functionality.
Solution Approach 2:
The patent changes the voltage parameters by using medium-voltage transistors instead of high-voltage transistors for the column-select device. This parameter change enables the transistor to operate at lower voltages during programming, thereby reducing the harmful GIDL stress and background leakage effects while still achieving the required programming effect.
2Reliability
If a high-voltage transistor is used for column selection, then programming can be performed, but large-area well boundaries are required
Solution Approach 1:
The patent changes the voltage parameter of the column-select transistor from high-voltage to medium-voltage operation. This parameter change allows the transistor to be implemented with smaller well boundaries, reducing the area required for well isolation while maintaining the programming capability.
3Reliability
If sector-based column select scheme is employed, then programming can be controlled, but device complexity increases
Solution Approach 1:
The patent segments the memory array into multiple blocks, each with its own source-side column-select transistor. This segmentation allows for more granular control of programming operations, enabling finer sector-based programming while reducing the complexity of the overall column select architecture by using simpler medium-voltage transistors.
Data Source
AI summary
A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.