Efuse Cell Array Redundancy Correction Circuit
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Solution Overview
Problem
Conventional efuse cells face issues with incorrect logic value outputs due to unbroken links or excessively small resistances during programming, requiring large redundant regions for correction, which complicates circuit and layout designs and reduces reliability.
Innovation Solution
A fuse link programming cell array is introduced, comprising two efuse cells and a mode control transistor, with a control circuit including AND gates and an inverter, allowing for two read operation modes to enable redundancy correction, where odd-column efuse cells function as storage bits and adjacent even-column cells act as redundancy, optimizing storage capacity and correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional efuse cells are used with indirect correction method, then error correction capability is achieved, but redundant region size increases significantly and circuit complexity increases
Solution Approach 1:
The efuse cell is segmented into two distinct parts: storage bits (odd columns) and redundancy correction bits (even columns). Each bit line connects to exactly one efuse cell, and each efuse cell has dedicated read and programming control transistors. This segmentation allows the system to achieve error correction capability while maintaining simpler circuit design compared to conventional indirect correction methods that require large redundant regions.
2Reliability
If large redundant region is allocated for error correction, then reliability improves, but actual storage capacity decreases
Solution Approach 1:
Different regions of the efuse cell array are assigned different functions with optimized characteristics. Odd-column efuse cells are designated as storage bits with full read and programming capabilities, while even-column efuse cells are designated as redundancy correction bits with simplified structures. This local quality differentiation allows the system to achieve error correction while maximizing actual storage capacity by not requiring excessively large redundant regions.
3Ease of manufacture
If conventional efuse cell structure is used, then manufacturing is simple, but programming reliability deteriorates due to unbroken links or excessively small resistance
Solution Approach 1:
The invention uses even-column efuse cells as copies/redundancy for odd-column storage bits. These redundancy cells are structured identically to storage cells but serve a different purpose. During programming, both storage and redundancy cells are programmed together, ensuring that if a storage bit fails to break its link or produces excessively small resistance, the corresponding redundancy bit can correct the error during read operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the flexibility of efuse cell arrays by implementing redundancy correction, reducing the physical storage region needed for redundancy, thereby increasing the actual storage capacity and improving the reliability of read and write operations.
Implementation Method 1
Based on the principle of electronic migration (EM), eFuse realizes a programming function by means of link fusion
Implementation Method 2
a read module inside the efuse converts a link resistance into a corresponding logic value, and a specific principle is that a comparison circuit compares the link resistance with a reference resistance
Data Source
AI summary
A fuse programming unit, comprising: two efuse units and a mode control tube. The first efuse unit includes: one end of the first fuse forms the first end, and the second end is connected to the drain end of the first MOS. The first MOS source terminal is grounded, and the first word line formed by the gate terminal. The second efuse unit includes: the first end of the second fuse forms the second wire end, and the second end is connected to the drain end of the second MOS. The second MOS source terminal is grounded, and the gate terminal forms the second line. The source end of the mode control transistor is connected to the line end of the second efuse unit, the drain end is connected to the source end of the first MOS, and the gate end forms the correction end.