Semiconductor Memory Erase via GIDL Current and Select Line Voltage Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving improved erase operation speed and reliability, particularly due to variations in junction overlaps between source select lines and common source lines, which affect erase speed and reliability.
Innovation Solution
The semiconductor memory device employs a method where a first voltage is applied to select lines to generate a gate-induced drain leakage (GIDL) current, and the voltage of adjacent select lines is increased by coupling an erase voltage to the common source line, ensuring that source select transistors are turned on, thereby forming a high electric field and enhancing erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional erase operation is performed without selective voltage application, then the erase operation is simple to implement, but the erase speed and reliability vary significantly due to junction overlap variations
Solution Approach 1:
The patent applies different voltage levels to different groups of second select lines based on their position relative to the common source line. Specifically, a first voltage is applied to first group second select lines, a second voltage is applied to second group second select lines, and a third voltage is applied to third group second select lines. This localized voltage control compensates for junction overlap variations in different regions, ensuring uniform erase performance across all cell strings regardless of their position.
2Productivity
If the voltage of second select lines is increased by coupling erase voltage to common source line, then the electric field is enhanced and erase efficiency is improved, but the voltage control becomes more complex
Solution Approach 1:
The patent pre-charges the second select lines to appropriate voltage levels before applying the erase voltage to the common source line. The first group second select lines are pre-charged to a first voltage, the second group second select lines are pre-charged to a second voltage, and the third group second select lines are pre-charged to a third voltage. This preliminary voltage application ensures that when the erase voltage is subsequently applied to the common source line, the desired electric field distribution is already established, enabling high-speed erase operation.
3Reliability
If ground voltage is applied to second select lines, then GIDL current is generated in source select transistors, but the erase speed varies due to junction overlap differences
Solution Approach 1:
The patent divides the second select lines into three groups and applies different voltage levels to each group based on their position relative to the common source line. The first group second select lines receive a first voltage, the second group second select lines receive a second voltage, and the third group second select lines receive a third voltage. This localized voltage control compensates for junction overlap variations in different regions, ensuring uniform erase speed across all cell strings while maintaining GIDL current generation for reliable erasure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the difference in erase speed between cell strings with varying junction overlaps, improving the reliability and speed of the erase operation by generating a GIDL current and maintaining it during the erase process.
Implementation Method 1
the first voltage may generate a gate induced drain leakage (GIDL) current in the second select transistors connected to the second select lines in the first group
Implementation Method 2
as the erase voltage is applied to the common source line, a voltage of the second group among the second select lines may be increased by coupling
Data Source
AI summary
A semiconductor memory device includes a memory string and a control logic. The memory string is connected between a common source line and a bit line and includes at least one first select transistor, a plurality of memory cells, and a plurality of second select transistors. The control logic is configured to apply a first voltage to a first group among second select lines respectively connected to the second select transistors, float a second group among the second select lines and then apply an erase voltage to the common source line, during an erase operation.