FinFET Memory Word Line Shielding Voltage
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Solution Overview
Problem
As memory devices are miniaturized, adjacent word lines in memory arrays can become capacitively coupled, leading to undesired programming, erasing, or reading of adjacent cells, particularly in non-planar transistors like FinFETs, due to close proximity despite insulating materials between them.
Innovation Solution
The implementation of independent gate structures with a planar layer and nitride portions in FinFET transistors, allowing for separate gate formation without extra masking steps and minimizing capacitive coupling by using a shielding voltage on adjacent word lines during operations like programming, erasing, and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory devices are miniaturized to decrease die size, then area efficiency is improved, but capacitive coupling between adjacent word lines increases causing undesired programming/erasing
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate and second gate) that can be independently controlled. This segmentation allows selective application of voltages to different gate regions, enabling precise control over which memory cells are accessed while minimizing capacitive coupling effects on adjacent cells. The independent gates can be biased differently to cancel out coupling effects.
Solution Approach 2:
An intermediate structure (such as a charge storage layer or insulating layer) is introduced between the gate and channel region. This intermediary layer acts as a buffer that reduces direct capacitive coupling between adjacent word lines while still allowing the gate to control the channel when properly biased. The intermediary structure decouples the electrical interaction between neighboring cells.
2Reliability
If independent gate structures are implemented to reduce capacitive coupling, then cell operation reliability is improved, but device complexity increases
Solution Approach 1:
The independent gate structure serves multiple functions: it provides selective cell access control, reduces capacitive coupling effects, and enables advanced programming/erasing schemes. By making the gate structure multi-functional, the added complexity is justified by the multiple benefits gained from a single structural modification rather than requiring separate mechanisms for each function.
Solution Approach 2:
The independent gate structures are merged with the existing FinFET transistor architecture, sharing common elements such as the channel region, source/drain structures, and interconnect layers. This integration approach allows the independent gates to be formed using modified versions of existing manufacturing processes rather than requiring entirely new process steps, thereby reducing the net increase in device complexity.
3Productivity
If adjacent word lines are placed closer together to increase memory density, then storage capacity is improved, but capacitive coupling causes undesired cell programming/erasing
Solution Approach 1:
Different voltage conditions are applied to different regions of the gate structure. The independent gates can be biased with different voltages depending on the local operation requirements - for example, one gate may be at programming voltage while the other is at a compensating voltage to cancel coupling effects on adjacent cells. This local differentiation of electrical conditions allows high density placement while mitigating coupling harm.
Solution Approach 2:
The electrical parameters (voltages) of the independent gates are dynamically changed during operation to compensate for capacitive coupling effects. By adjusting the gate voltages based on the operation being performed (read, program, erase), the system can maintain correct cell states even when word lines are closely spaced. Parameter modulation allows the system to adapt to the coupling conditions created by high-density placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitive coupling between adjacent word lines, allowing for reliable and independent operation of memory cells with lower programming voltages and reduced area requirements for circuitry, enhancing the reliability and efficiency of memory arrays.
Implementation Method 1
the word line that is adjacent the selected word line may undesirably become capacitively coupled to the selected word line. Although an insulating material lies between the two word lines, the distance between them may be small enough to enable coupling.
Implementation Method 2
minimizing capacitive coupling by using a shielding voltage on adjacent word lines during operations like programming, erasing, and reading
Data Source
AI summary
A method for operating a memory device includes selecting a cell comprising an array of word lines, selecting a word line within said array and applying an operating voltage to said selected word line. A shielding voltage is also applied to the closest adjacent facing word line of said selected word line. This may prevent unintended, program, read, or erase of said unselected word line. The remainder of unselected word lines can be floated.