NAND Flash Memory Bit Line Pre-Charging for Peak Current Suppression
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Solution Overview
Problem
In NAND flash memory, the large parasitic capacitance and simultaneous pre-charging of bit lines lead to a significant peak current, causing power voltage drops during reading operations, particularly affecting low power devices and leading to operational failures.
Innovation Solution
The semiconductor storage device employs a method where the sense node and bit line are pre-charged in multiple stages, using a pre-charging transistor and a clamp transistor to distribute the current, reducing peak current noise and preventing power voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all bit lines are pre-charged simultaneously, then the reading operation can be performed, but a large peak current flows causing power voltage drops
Solution Approach 1:
The pre-charging operation is segmented into multiple stages: first pre-charging the sense node, then pre-charging the bit line node to a first clamp voltage, and finally pre-charging to a second clamp voltage. This segmentation divides the single large current event into multiple smaller current events, preventing power voltage drops while maintaining reading functionality.
Solution Approach 2:
The sense node is pre-charged before the bit line node, and the bit line node is pre-charged to intermediate clamp voltages before the final reading voltage. These preliminary actions prepare the circuit in stages, avoiding sudden large current draws that would cause power voltage instability.
2Quantity of substance
If the bit line capacitance increases due to more pages, then more data can be stored, but the charging time becomes longer
Solution Approach 1:
The pre-charging is performed as periodic staged actions with specific timing: first pre-charging the sense node, then pre-charging the bit line to first clamp voltage, and finally to second clamp voltage. This periodic multi-stage approach manages the increased capacitance load efficiently without extending total reading time excessively.
3Productivity
If miniaturization increases bit line resistance, then device density improves, but charging/discharging time increases
Solution Approach 1:
The sense node is pre-charged before the bit line, and the bit line is pre-charged to intermediate clamp voltages before final operation. These preliminary actions reduce the effective voltage swing required during actual reading, compensating for the increased resistance from miniaturization and reducing overall charging time.
Data Source
AI summary
The invention provides a semiconductor memory device and a reading method thereof, which are capable of suppressing a peak current when pre-charging a bit line are provided. The reading method of a flash memory of the present invention includes steps of: pre-charging a selected bit line; and reading a voltage or a current of the pre-charged selected bit line. The step of pre-charging is performed by pre-charging a sense node SNS to Vcc−Vth at a time t1, pre-charging a node TOBL to VCLAMP2 at a time t2, pre-charging the node TOBL to VCLAMP1 at a time t5, and pre-charging the sense node SNS to Vcc at a time t6.