EEPROM Memory Architecture for Embedded Applications
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Solution Overview
Problem
Conventional EEPROM and Flash memory architectures face challenges in balancing word-erasability and high density, leading to longer read access times and higher electrical consumption due to parasitic capacitance and crosstalk issues, which are not optimally addressed in embedded memory applications that require both program and application data storage.
Innovation Solution
An electrically erasable and programmable memory architecture that includes rows of memory cells with interconnected control gate terminals for collective erasability and individually erasable words, using a Flash-like structure to reduce parasitic capacitance and crosstalk, with sense amplifiers connected through word selection transistors to adjacent bit lines, optimizing for embedded memory applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional EEPROM architecture is used, then word-erasability is achieved, but parasitic capacitance increases and read access time lengthens
Solution Approach 1:
The memory array is segmented into multiple blocks, where each block contains a subset of columns. Sense amplifiers are assigned to specific blocks, allowing parallel read operations across different blocks. This segmentation reduces the effective capacitance each sense amplifier must handle, thereby reducing read access time while preserving word-erasability through the floating-gate transistor architecture.
Solution Approach 2:
The patent introduces a block dimension to the traditional row-column memory organization. By dividing columns into blocks and assigning sense amplifiers to specific blocks, the patent creates a three-dimensional addressing structure (row, block, column) that reduces parasitic capacitance effects during read operations while maintaining the word-erasable capability.
2Adaptability or versatility
If conventional EEPROM architecture is used, then word-erasability is achieved, but electrical consumption increases due to parasitic capacitance
Solution Approach 1:
The memory is divided into blocks with dedicated sense amplifiers, reducing the total capacitance that must be charged/discharged during read operations. This segmentation directly reduces electrical consumption while preserving the word-erasable function through the floating-gate transistor structure.
3Quantity of substance
If Flash memory architecture is used, then high density is achieved, but page-erasability is limited and word-erasability is lost
Solution Approach 1:
The patent merges the Flash memory single-transistor high-density cell structure with the EEPROM floating-gate transistor's word-erasable capability. By controlling the control gate voltage of the floating-gate transistor, the patent enables selective word-erasable operation while maintaining the high density of Flash memory architecture.
Solution Approach 2:
The patent introduces dynamic control of the floating-gate transistor's control gate to enable word-erasable operation. By dynamically adjusting the control gate voltage, the patent can selectively erase individual words or groups of words while maintaining the high-density Flash memory structure, making the erasability characteristic adjustable rather than fixed.
4Area of stationary object
If sense amplifiers are connected through long multiplexing lines, then memory coverage is increased, but parasitic capacitance increases and read access time lengthens
Solution Approach 1:
The patent divides the memory into blocks, each served by dedicated sense amplifiers located within or near the block. This eliminates the need for long multiplexing lines spanning the entire memory array, as sense amplifiers only need to connect to nearby bit lines within their assigned block, significantly reducing parasitic capacitance and read access time while maintaining full memory coverage through block-level parallelism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture reduces parasitic capacitance, minimizes crosstalk, and enhances read access times while lowering electrical consumption, enabling efficient storage of both program and application data in embedded memory applications.
Implementation Method 1
a floating gate transistor having a control gate terminal to receive an erase voltage
Data Source
AI summary
The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word.