Page Buffer Circuit Dynamic Latch Refresh via Charge Sharing
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Solution Overview
Problem
Conventional page buffer circuits in semiconductor memory devices face challenges in efficiently refreshing data stored in dynamic latch circuits without additional latch circuits, leading to data distortion due to leakage currents and limited retention times.
Innovation Solution
The proposed page buffer circuit employs a dynamic latch circuit with charge sharing between a storage node and a sensing node, and additional sensing node sharing transistors that connect multiple page buffers, allowing for efficient data refresh operations without the need for additional latch circuits, thereby improving retention times and data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a dynamic latch circuit is used to reduce size and power consumption, then device area and power usage are reduced, but data retention time decreases and data distortion occurs due to leakage currents
Solution Approach 1:
The sensing node is precharged to a predetermined voltage level before the refresh operation begins. This preliminary action ensures that when charge sharing occurs with the storage node, the dynamic latch circuit can be properly refreshed even though it has limited retention time due to leakage currents.
Solution Approach 2:
The sensing node acts as an intermediary between the bitline and the storage node of the dynamic latch circuit. During the refresh operation, the sensing node transfers charge to the storage node through controlled charge sharing, enabling data refresh without requiring an additional dedicated latch circuit.
2Duration of action of stationary object
If charge sharing is used to refresh data in dynamic latch circuits, then data retention is improved, but additional circuit elements are required
Solution Approach 1:
The sensing node is designed to serve multiple functions: it acts as a sensing element during read operations, as a precharge element during refresh operations, and as a charge transfer medium during write operations. This multi-functionality eliminates the need for additional dedicated latch circuits, maintaining circuit simplicity while improving data retention.
Solution Approach 2:
The refresh function is merged with the existing sensing node and bitline structure. By combining the refresh operation with the read/write pathway, the patent avoids adding separate refresh circuitry, thus improving data retention without significantly increasing device complexity.
3Area of stationary object
If multiple page buffers share sensing nodes, then circuit area is reduced, but interference between adjacent page buffers may occur
Solution Approach 1:
The connection between adjacent page buffers' sensing nodes is dynamically controlled through the sensing node sharing signal. When refreshing, the sensing nodes of adjacent page buffers are temporarily connected to share charge. During normal read/write operations, these connections are disconnected, preventing interference. This dynamic switching ensures both area efficiency and data accuracy.
Solution Approach 2:
The sensing node sharing is implemented selectively between adjacent page buffers that require refresh operations, rather than universally across all page buffers. This localized sharing approach minimizes potential interference while still achieving area reduction benefits where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient data refresh in dynamic latch circuits, enhancing data retention times and reducing power consumption by eliminating the need for additional latch circuits, while maintaining data accuracy through charge sharing mechanisms.
Implementation Method 1
Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node
Implementation Method 2
a precharge circuit configured to precharge the sensing node
Data Source
AI summary
A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.


