Multi-Level Memory Page Buffer Latch Control for Read Speed
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Solution Overview
Problem
Conventional multi-level nonvolatile semiconductor memory devices require a lengthy sequence of precharge operations for bit line sensing, which increases the time required to read data.
Innovation Solution
A nonvolatile semiconductor memory device with a page buffer that includes a main data latch and a sub-data latch, where the flipping of the main data latch is inhibited based on the logic state of the sub-data latch, and a latch control block that selectively flips the main data latch depending on the voltage level of the bit line, allowing for primary and secondary mapping of threshold voltages using first and third reference voltages to reduce the number of bit line precharge operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional multi-level nonvolatile semiconductor memory devices perform a complete sequence of precharge operations for bit line sensing, then measurement precision is maintained, but loss of time increases due to lengthy read operations
Solution Approach 1:
The patent applies partial action by performing only necessary precharge operations based on the threshold voltage group being read. When reading from the first threshold voltage group, only the first bit line is precharged. When reading from the second threshold voltage group, both first and second bit lines are precharged. This selective precharging maintains measurement precision while reducing unnecessary precharge operations, thereby decreasing data read time.
2Loss of time
If the number of bit line precharge operations is reduced, then loss of time decreases, but measurement precision may deteriorate due to insufficient precharging
Solution Approach 1:
The patent implements dynamic precharging by adapting the number of precharge operations to the specific reading requirements. The control logic dynamically determines which bit lines need precharging based on the target threshold voltage group. This dynamic approach ensures sufficient precharging for the specific operation while avoiding unnecessary precharges, thereby maintaining precision while reducing time loss.
3Productivity
If multi-level memory cells are implemented to increase storage capacity, then productivity increases, but device complexity increases due to multiple threshold voltage groups and reference voltages
Solution Approach 1:
The patent applies segmentation by dividing the memory cell operations into distinct segments: first threshold voltage group operations using first reference voltage and first bit line, and second threshold voltage group operations using second reference voltage and second bit line. This segmentation allows the complex multi-level memory to be managed through modular, independent operation sequences, reducing the perceived complexity while maintaining high storage capacity.
Solution Approach 2:
The patent introduces an additional operational dimension by implementing dual bit lines (first and second bit lines) and dual reference voltages (first and second reference voltages). This dimensional expansion allows simultaneous handling of multiple threshold voltage groups, enabling the memory device to achieve high storage capacity while managing complexity through parallel operational pathways.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the number of bit line precharge operations, thereby shortening the time required to read data from multi-level memory cells.
Implementation Method 1
The electrons moving to the floating gate FG are generated by Fowler-Nordheim tunneling (FN), electron injection, etc.
Implementation Method 2
The electrons moving to the floating gate FG are generated by Fowler-Nordheim tunneling (FN), electron injection, etc.
Implementation Method 3
When the nonvolatile semiconductor memory device performs a read operation, the data value stored in memory cell MC is determined by sensing the threshold voltage of memory cell MC.
Data Source
AI summary
A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.