Flash Memory Verification Voltage Adjustment for Programming Uniformity
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Solution Overview
Problem
Conventional flash memory technologies face inefficiencies due to varying sensing parasitic resistances across memory cells, leading to uneven programming and erasing verification windows, which result in decreased programming uniformity and wasted operating windows.
Innovation Solution
A method is introduced that applies different verifying voltages based on the sensing parasitic resistance of each memory cell, ensuring equal memory operating windows and threshold voltage differences after verification, thereby enhancing programming and erasing uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional verification is applied to all memory cells with a single verification voltage, then the verification process is simple, but memory cells with different sensing parasitic resistances experience uneven verification windows leading to decreased programming uniformity
Solution Approach 1:
The patent applies different verification voltages to different groups of memory cells based on their sensing parasitic resistance characteristics. Memory cells are divided into first and second groups, with each group receiving a tailored verification voltage (first verification voltage for the first group, second verification voltage for the second group). This local differentiation ensures that each group experiences an equal verification window, improving programming uniformity without requiring complete redesign of the verification architecture.
Solution Approach 2:
The patent changes the verification voltage parameter according to the sensing parasitic resistance of different memory cell groups. By adjusting the verification voltage to compensate for the array resistance effect in different groups, the patent equalizes the verification windows across all memory cells. This parameter adaptation allows the system to maintain simple verification procedures while achieving uniform programming results.
2Manufacturing precision
If different verification voltages are applied to different memory cell groups, then programming uniformity is improved, but the verification process becomes more complex
Solution Approach 1:
The patent segments memory cells into distinct groups (first group and second group) based on their sensing parasitic resistance characteristics. Each segment is then subjected to a customized verification voltage appropriate for its resistance profile. This segmentation approach allows the complex verification process to be broken down into manageable, standardized sub-processes that can be implemented through systematic grouping and corresponding voltage selection.
3Quantity of substance
If a single verification voltage is used for all memory cells, then the verification process is straightforward, but memory operating window is wasted due to uneven verification windows
Solution Approach 1:
The patent implements local quality by assigning different verification voltages to different memory cell groups based on their specific sensing parasitic resistance characteristics. This ensures that each group utilizes its full memory operating window effectively, preventing the waste that occurs when a single verification voltage is used for all cells. The first verification voltage optimizes the first group's window utilization while the second verification voltage does the same for the second group.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains consistent memory operating windows and threshold voltage differences, ensuring accurate programming and erasing without affecting practical operations, thereby improving the uniformity and efficiency of flash memory operations.
Implementation Method 1
The sense amplifier 120 is for detecting the cell current of the memory cells M to ascertain whether the memory cells M succeeds in programming
Data Source
AI summary
A method for determing the logic state of a memory cell of an array is provided. The array includes many word lines and bit lines. The method proceeds with the following steps. Firstly, a first voltage varing according to a sensing parasitic resistance of the memory cell is applied to the memory cell for a cell current. Next, a second voltage is applied to a reference cell corresponding to the memory cell for a reference current. Then, the cell current is compared with the reference current so as to determine the logic state of the memory cell.